Dinesh Gaitonde
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
6
Active years
1999–2026
Best venue rank
A
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | FCCM | PathSteiner: Improving PathFinder with Quasi-Optimal Steiner-Tree Initialization. | Shashwat Shrivastava, Luka Kuresevic, Alexandros Poupakis, Chirag Ravishankar, Dinesh Gaitonde, Stefan Nikolic, Mirjana Stojilovic |
| 2025 | FCCM | Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox. | Shashwat Shrivastava, Stefan Nikolic, Sun Tanaka, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic |
| 2023 | FCCM | Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. | Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde |
| 2023 | FPGA | Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. | Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic |
| 2023 | ICCAD | IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. | Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic |
| 2020 | FPL | A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. | Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde |
| 2019 | FPGA | Xilinx Adaptive Compute Acceleration Platform: Versal | Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer |
| 2019 | FPGA | Network-on-Chip Programmable Platform in Versal | Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Brian Gaide, Ygal Arbel |
| 2019 | HOTI | Versal Network-on-Chip (NoC). | Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Bala Jayadev, Jeff Cuppett, Abbas Morshed, Brian Gaide, Ygal Arbel |
| 2018 | FPL | A SAT-based Timing Driven Place and Route Flow for Critical Soft IP. | Henri Fraisse, Dinesh Gaitonde |
| 2018 | FPL | Placement Strategies for 2.5D FPGA Fabric Architectures. | Chirag Ravishankar, Dinesh Gaitonde, Trevor Bauer |
| 2016 | FPGA | Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network. | Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani |
| 2015 | FPGA | Enhancements in UltraScale CLB Architecture. | Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer |
| 1999 | ISCAS | Instruction level power model of microcontrollers. | Chaitali Chakrabarti, Dinesh Gaitonde |