| 2004 | VTS | Memory BIST Using ESP. | Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk |
| 2000 | ITC | Conversion of small functional test sets of nonscan blocks to scan patterns. | Don E. Ross, Tim Wood, Grady Giles |
| 1995 | VLSID | Efficient variable ordering and partial representation algorithm. | Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross |
| 1994 | VTS | Linear finite state machine for lD ILAs. | Murali M. R. Gala, Peter Utama, Don E. Ross, Karan L. Watson |
| 1993 | ISCAS | An Accurate Delay Model for BiCMOS Gates and Off-chip Drivers. | Sherif H. K. Embabi, R. Damodaran, R. Bhagwan, Don E. Ross |
| 1993 | VTS | Testability of one dimensional ILAs under multiple faults. | Murali M. R. Gala, Karan L. Watson, Don E. Ross |
| 1993 | VTS | Signal probability calculations using partial functional manipulation. | Ravishankar Kodavarti, Don E. Ross |
| 1993 | VTS | LFSR based deterministic hardware for at-speed BIST. | Beena Vasudevan, Don E. Ross, Murali M. R. Gala, Karan L. Watson |
| 1992 | DAC | Functional Approaches to Generating Orderings for Efficient Symbolic Representations. | M. Ray Mercer, Rohit Kapur, Don E. Ross |
| 1992 | VTS | The roles of controllability and observability in design for test. | Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross |
| 1991 | DAC | Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. | Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer |
| 1988 | DAC | CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. | Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler |