| 2020 | ICDCS | Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory. | Tao Luo, Wei Zhang, Bingsheng He, Cheng Liu, Douglas L. Maskell |
| 2020 | ISCAS | High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. | Xiangwei Li, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain |
| 2018 | DATE | A time-multiplexed FPGA overlay with linear interconnect. | Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy |
| 2018 | Tencon | A System Health Indicator for the Distributed Minority and Majority Voting Based Redundancy Scheme. | P. Balasubramanian, Douglas L. Maskell, Krishnamachar Prasad |
| 2018 | Tencon | Hardware Efficient Approximate Adder Design. | P. Balasubramanian, Douglas L. Maskell |
| 2017 | ICCAD | A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography. | Tao Luo, Bingsheng He, Wei Zhang, Douglas L. Maskell |
| 2016 | ASPDAC | A racetrack memory based in-memory booth multiplier for cryptography application. | Tao Luo, Wei Zhang, Bingsheng He, Douglas L. Maskell |
| 2016 | DASC | Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? | Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy |
| 2016 | DATE | Throughput oriented FPGA overlays using DSP blocks. | Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy |
| 2016 | FCCM | DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. | Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy |
| 2015 | FCCM | Efficient Overlay Architecture Based on DSP Blocks. | Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell |
| 2015 | IJCNN | Automatic fault detection and diagnosis for photovoltaic systems using combined artificial neural network and analytical based methods. | Lian Lian Jiang, Douglas L. Maskell |
| 2014 | IECON | Soft-switching single inductor current-fed push-pull converter for PV applications. | D. R. Nayanasiri, D. Mahinda Vilathgamuwa, Douglas L. Maskell, Gilbert Hock Beng Foo |
| 2013 | IECON | A simple and efficient hybrid maximum power point tracking method for PV systems under partially shaded condition. | Lian Lian Jiang, D. R. Nayanasiri, Douglas L. Maskell, D. Mahinda Vilathgamuwa |
| 2013 | IECON | High-frequency-link micro-inverter with front-end current-fed half-bridge boost converter and half-wave cycloconverter. | D. R. Nayanasiri, D. Mahinda Vilathgamuwa, Douglas L. Maskell |
| 2012 | FPGA | A lean FPGA soft processor built using a DSP block. | Hui Yan Cheah, Suhaib A. Fahmy, Douglas L. Maskell, Chidamber Kulkarni |
| 2012 | FPGA | Accelerating short read mapping on an FPGA (abstract only). | Yupeng Chen, Bertil Schmidt, Douglas L. Maskell |
| 2012 | FPL | An FPGA aligner for short read mapping. | Yupeng Chen, Bertil Schmidt, Douglas L. Maskell |
| 2012 | ICASSP | A flann-based controller for maximum power point tracking in PV systems under rapidly changing conditions. | Lian Lian Jiang, Douglas L. Maskell, Jagdish Chandra Patra |
| 2012 | IJCNN | Chebyshev Functional Link Neural Network-based modeling and experimental verification for photovoltaic arrays. | Lian Lian Jiang, Douglas L. Maskell, Jagdish Chandra Patra |
| 2011 | SMC | Estimation of external quantum efficiency for multi-junction solar cells under influence of charged particles using artificial neural networks. | Jagdish Chandra Patra, Lian Lian Jiang, Douglas L. Maskell |
| 2010 | ASPDAC | High level event driven thermal estimation for thermal aware task allocation and scheduling. | Jin Cui, Douglas L. Maskell |
| 2010 | FPGA | A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only). | Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell |
| 2009 | ICCS | Workshop on Using Emerging Parallel Architectures for Computational Science. | Bertil Schmidt, Douglas L. Maskell |
| 2008 | MMSP | Multiplierless multi-standard SDR channel filters. | Douglas L. Maskell, Achutavarrier Prasad Vinod, Graham S. Woods |
| 2007 | CEC | Type-2 GA-TSK fuzzy neural network. | Alvin Cai, Chai Quek, Douglas L. Maskell |
| 2007 | ICPADS | An Embedded Systems graduate education for Singapore. | Ian McLoughlin, Douglas L. Maskell, Thambipillai Srikanthan, Wooi-Boon Goh |
| 2006 | CEC | FCMAC-AARS: A Novel FNN Architecture for Stock Market Prediction and Trading. | Zaiyi Guo, Chai Quek, Douglas L. Maskell |
| 2006 | CEC | A Brain Inspired Fuzzy Neuro-predictor for Bank Failure Analysis. | Chee H. Lee, Chai Quek, Douglas L. Maskell |
| 2006 | FPL | Execution Objects for Dynamically Reconfigurable FPGA Systems. | Timothy F. Oliver, Douglas L. Maskell |
| 2006 | FPL | Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. | K. S. Tham, Douglas L. Maskell |
| 2006 | ICCS | Accelerating the Viterbi Algorithm for Profile Hidden Markov Models Using Reconfigurable Hardware. | Timothy F. Oliver, Bertil Schmidt, Yanto Jakop, Douglas L. Maskell |
| 2006 | ISCAS | The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity. | Douglas L. Maskell, Jussipekka Leiwo, Jagdish Chandra Patra |
| 2005 | FPGA | Hyper customized processors for bio-sequence database scanning on FPGAs. | Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell |
| 2005 | ICPADS | Multiple Sequence Alignment on an FPGA. | Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell, Darran Nathan, Ralf Clemens |
| 2005 | ISCAS | A reconfigurable architecture for scanning biosequence databases. | Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell, Achutavarrier Prasad Vinod |
| 2004 | ISCAS | A hardware efficient implementation of an adaptive subsample delay estimator. | Douglas L. Maskell, Graham S. Woods, Andrew Kerans |