| 2023 | ARITH | Improved Montgomery Multiplication. | Trenton J. Grale, Earl E. Swartzlander Jr. |
| 2019 | ACSSC | A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing. | Alexander J. Groszewski, Earl E. Swartzlander Jr. |
| 2017 | ACSSC | Parallel GF(2 | Trenton J. Grale, Earl E. Swartzlander Jr. |
| 2017 | ACSSC | The future of computing - Arithmetic circuits implemented with memristors. | Nagaraja Revanna, Lauren Guckert, Earl E. Swartzlander Jr. |
| 2016 | ACSSC | Optimized memristor-based ripple carry adders. | Lauren Guckert, Earl E. Swartzlander Jr. |
| 2016 | ACSSC | Memristor based adder circuit design. | Nagaraja Revanna, Earl E. Swartzlander Jr. |
| 2015 | ACSSC | Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow). | Robert J. Ascott, Earl E. Swartzlander Jr. |
| 2015 | ACSSC | Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication. | Mike O'Connor, Earl E. Swartzlander Jr. |
| 2015 | ARITH | Low-Cost Duplicate Multiplication. | Michael B. Sullivan, Earl E. Swartzlander Jr. |
| 2014 | ACSSC | Improved non-restoring square root algorithm with dual path calculation. | Kihwan Jun, Earl E. Swartzlander Jr. |
| 2014 | ACSSC | Memristor based adders. | Divya Mahajan, Matheen Musaddiq, Earl E. Swartzlander Jr. |
| 2013 | ACSSC | Implementation of a high speed multiplier using carry lookahead adders. | Wesley Chu, Ali I. Unwala, Pohan Wu, Earl E. Swartzlander Jr. |
| 2013 | ACSSC | On separable error detection for addition. | Michael B. Sullivan, Earl E. Swartzlander Jr. |
| 2013 | ARITH | Improved Architectures for a Floating-Point Fused Dot Product Unit. | Jongwook Sohn, Earl E. Swartzlander Jr. |
| 2013 | ARITH | Truncated Logarithmic Approximation. | Michael B. Sullivan, Earl E. Swartzlander Jr. |
| 2013 | ISCAS | Power analysis attack of QCA circuits: A case study of the Serpent cipher. | Weiqiang Liu, Saket Srivastava, Liang Lu, Mire O'Neill, Earl E. Swartzlander Jr. |
| 2012 | ACSSC | Modified non-restoring division algorithm with improved delay profile and error correction. | Kihwan Jun, Earl E. Swartzlander Jr. |
| 2012 | ACSSC | A review of QCA adders and metrics. | Weiqiang Liu, Mire O'Neill, Earl E. Swartzlander Jr. |
| 2012 | ACSSC | A low-power dual-path floating-point fused add-subtract unit. | Jae Hong Min, Jongwook Sohn, Earl E. Swartzlander Jr. |
| 2012 | ACSSC | Truncated error correction for flexible approximate multiplication. | Michael B. Sullivan, Earl E. Swartzlander Jr. |
| 2012 | ISCAS | Cost-efficient decimal adder design in Quantum-dot cellular automata. | Weiqiang Liu, Liang Lu, Mire O'Neill, Earl E. Swartzlander Jr. |
| 2011 | ACSSC | A floating-point fused FFT butterfly arithmetic unit with Merged Multiple-Constant Multipliers. | Jae Hong Min, Seong-Wan Kim, Earl E. Swartzlander Jr. |
| 2011 | ACSSC | The fully-serial pipelined multiplier. | Andrew G. Shafer, Lyndsi R. Parker, Earl E. Swartzlander Jr. |
| 2011 | ACSSC | Hybrid residue generators for increased efficiency. | Michael B. Sullivan, Earl E. Swartzlander Jr. |
| 2011 | ISCAS | Design rules for Quantum-dot Cellular Automata. | Weiqiang Liu, Liang Lu, Mire O'Neill, Earl E. Swartzlander Jr. |
| 2010 | ICASSP | A novel technique for tunable mismatch shaping in oversampled digital-to-analog converters. | Waqas Akram, Earl E. Swartzlander Jr. |
| 2008 | ACSSC | Fused floating-point arithmetic for DSP. | Earl E. Swartzlander Jr., Hani H. Saleh |
| 2008 | ACSSC | A rounding method with improved error tolerance for division by convergence. | Inwook Kong, Earl E. Swartzlander Jr. |
| 2008 | ICASSP | 32 bit single cycle nonlinear VLSI cell for the ICA algorithm. | Vijay K. Jain, Earl E. Swartzlander Jr. |
| 2008 | ICCD | A floating-point fused dot-product unit. | Hani H. Saleh, Earl E. Swartzlander Jr. |
| 2007 | ARITH | Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. | Heumpil Cho, Earl E. Swartzlander Jr. |
| 2007 | ICCD | Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. | Hani Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr. |
| 2005 | ARITH | Parallel Prefix Adder Design with Matrix Representation. | Youngmoon Choi, Earl E. Swartzlander Jr. |
| 2003 | ISCAS | A self-testing method for the pipelined A/D converter. | Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr. |
| 2001 | ARITH | Analysis of Column Compression Multipliers. | K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte |
| 2001 | ICASSP | Time-shared TMR for fault-tolerant CORDIC processors. | Jae-Hyuck Kwak, Vincenzo Piuri, Earl E. Swartzlander Jr. |
| 1999 | ICCD | High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. | Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr. |
| 1999 | ISCAS | Bipolar merged arithmetic for wavelet architectures. | Gwangwoo Choe, Earl E. Swartzlander Jr. |
| 1998 | ICCD | A reduction scheme to optimize the Wallace multiplier. | Moises E. Robinson, Earl E. Swartzlander Jr. |
| 1997 | ARITH | Power-Delay Characteristics of CMOS Multipliers. | Thomas K. Callaway, Earl E. Swartzlander Jr. |
| 1997 | ISLPED | Survey of low power techniques for ROMs. | Edwin de Angel, Earl E. Swartzlander Jr. |
| 1996 | ICASSP | Multidimensional systolic arrays for multidimensional DFTs. | Hyesook Lim, Earl E. Swartzlander Jr. |
| 1996 | ICASSP | Granularly-pipelined CORDIC processors for sine and cosine generators. | Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr. |
| 1995 | ARITH | Cascaded Implementation of an Iterative Inverse--Square--Root Algorithm, with Overflow Lookahead. | Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr. |
| 1995 | ARITH | Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor. | Michael J. Schulte, Earl E. Swartzlander Jr. |
| 1995 | ICCD | An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . | Hyesook Lim, Earl E. Swartzlander Jr. |
| 1995 | ICCD | A coprocessor for accurate and reliable numerical computations. | Michael J. Schulte, Earl E. Swartzlander Jr. |
| 1995 | ISCAS | Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks. | Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr. |
| 1995 | ISCAS | Fault-Tolerant Neural Architectures: The Use of Rotated Operands. | Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr. |
| 1995 | ISCAS | Merged CORDIC Algorithm. | Shaoyun Wang, Earl E. Swartzlander Jr. |
| 1995 | RSP | Rapid prototyping fault-tolerant heterogeneous digital signal processing systems. | Mohammad S. Khan, Earl E. Swartzlander Jr. |
| 1994 | ICCD | A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. | Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham |
| 1994 | ICPADS | What Types of Research Papers Should We Be Writing? | Thomas L. Casavant, Chi-Yuan Chin, Wen-Tsuen Chen, Kang G. Shin, Earl E. Swartzlander Jr., Joseph E. Urban |
| 1994 | ICPADS | Is It Possible to Fairly Compare Interconnection Networks?. | Jos Duato, C. T. Howard Ho, Ferng-Ching Lin, Lionel M. Ni, Earl E. Swartzlander Jr. |
| 1994 | ICPADS | Sorting Networks with Built-In Error Correction. | Yuang-Ming Hsu, Earl E. Swartzlander Jr. |
| 1994 | ICPADS | Heterogeneous Parallel Computing. | Earl E. Swartzlander Jr. |
| 1994 | ISCAS | A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors. | Mohammad S. Khan, Earl E. Swartzlander Jr. |
| 1993 | ARITH | Estimating the power consumption of CMOS adders. | Thomas K. Callaway, Earl E. Swartzlander Jr. |
| 1993 | ARITH | Exact rounding of certain elementary functions. | Michael J. Schulte, Earl E. Swartzlander Jr. |
| 1993 | ICCD | A Comparative Evaluation of Adders Based on Performance and Testability. | Rathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr. |
| 1993 | ISCAS | Superpipelined Adder Designs. | Ishaq H. Unwala, Earl E. Swartzlander Jr. |
| 1993 | RSP | Design and implementation of an interface control unit for rapid prototyping. | Mohammad S. Khan, Earl E. Swartzlander Jr. |
| 1992 | ICCD | Arithmetic Error Analysis of a new Reciprocal Cell. | Vijay K. Jain, Gibert E. Perez, Earl E. Swartzlander Jr. |
| 1992 | ICCD | Modified Booth Algorithm for High Radix Multiplication. | Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr. |
| 1991 | ARITH | The redundant cell adder. | Thomas W. Lynch, Earl E. Swartzlander Jr. |
| 1991 | ARITH | High-speed multiplier design using multi-input counter and compressor circuits. | Mayur Mehta, Vijay Parmar, Earl E. Swartzlander Jr. |
| 1991 | ARITH | Arithmetic for digital neural networks. | David Zhang, Graham A. Jullien, William C. Miller, Earl E. Swartzlander Jr. |
| 1985 | ARITH | Arithmetic for high speed FFT implementation. | Earl E. Swartzlander Jr., John A. Eldon |
| 1985 | ICASSP | Image processing address generator chip. | John A. Eldon, Zoltan Stroll, Earl E. Swartzlander Jr. |
| 1984 | ICASSP | Fast transform processor implementation. | Earl E. Swartzlander Jr., George Hallnor |
| 1983 | ICASSP | Digital signal processing with VLSI technology. | Earl E. Swartzlander Jr., Louis S. Lome, George Hallnor |
| 1980 | ICASSP | Signal processing architectures with VLSI. | Earl E. Swartzlander Jr. |
| 1978 | ARITH | Merged arithmetic for signal processing. | Earl E. Swartzlander Jr. |
| 1977 | MICRO | Microprogrammed control for signal processing. | Earl E. Swartzlander Jr. |