| 2025 | FPL | Compile in Seconds and Run on an FPGA with DynaRapid. | Andrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne |
| 2024 | FPL | DynaRapid: Fast-Tracking from C to Routed Circuits. | Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne |
| 2023 | DATE | Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. | Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek |
| 2023 | ICCAD | Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling. | Chris Lavin, Eddie Hung |
| 2019 | FCCM | EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation. | Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung |
| 2019 | FCCM | Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. | David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic |
| 2018 | ETS | Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. | Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton |
| 2017 | FPL | STRIPE: Signal selection for runtime power estimation. | James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides |
| 2016 | FCCM | KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. | Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides |
| 2016 | FPGA | Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). | James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides |
| 2015 | FCCM | Accelerating SpMV on FPGAs by Compressing Nonzero Values. | Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk |
| 2015 | FPGA | Delay-Bounded Routing for Shadow Registers. | Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk |
| 2015 | FPL | Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry. | Eddie Hung |
| 2014 | FPL | Transparent insertion of latency-oblivious logic onto FPGAs. | Eddie Hung, Tim Todman, Wayne Luk |
| 2013 | FCCM | Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. | Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton |
| 2013 | FPGA | Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. | Eddie Hung, Steven J. E. Wilton |
| 2012 | FPL | Limitations of incremental signal-tracing for FPGA debug. | Eddie Hung, Steven J. E. Wilton |
| 2011 | FPL | Speculative Debug Insertion for FPGAs. | Eddie Hung, Steven J. E. Wilton |
| 2008 | FPL | A configurable and programmable motion estimation processor for the H.264 video codec. | Jos Luis Nez-Yez, Eddie Hung, Vassilios A. Chouliaras |