Eduardo de la Torre
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
18
Venues
8
Active years
1993–2019
Best venue rank
B
Where they publish
Papers
18 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | FCCM | Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. | Rafael Zamacola, Alberto Garca-Martnez, Javier Mora, Andrs Otero, Eduardo de la Torre |
| 2017 | DATE | Cross-layer design of reconfigurable cyber-physical systems. | Michael Masin, Francesca Palumbo, Hans Myrhaug, J. A. de Oliveira Filho, M. Pastena, Maxime Pelcat, Luigi Raffo, Francesco Regazzoni, A. A. Sanchez, Antonella Toffetti, Eduardo de la Torre, Katiuscia Zedda |
| 2015 | ISCAS | Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. | Alfonso Rodrguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
| 2014 | FPL | A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. | Juan Valverde, Alfonso Rodrguez, Julio Camarero, Andrs Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
| 2014 | ISPEC | A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm. | Chenyang Tu, Wei He, Neng Gao, Eduardo de la Torre, Zeyi Liu, Limin Liu |
| 2013 | FPL | A self-adaptive image processing application based on evolvable and scalable hardware. | Angel Gallego, Javier Mora, Andrs Otero, Blanca Lpez, Eduardo de la Torre, Teresa Riesgo |
| 2012 | DSD | FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels. | Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Mihai T. Lazarescu, Eduardo de la Torre, Florian Schfer |
| 2012 | FPL | Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. | Rubn Salvador, Andrs Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Luks Sekanina |
| 2011 | FPL | Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. | Andrs Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastin Lpez, Gustavo M. Callic, Roberto Sarmiento |
| 2010 | DSD | A Modular Peripheral to Support Self-Reconfiguration in SoCs. | Andrs Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
| 2010 | FPL | Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. | Andrs Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva |
| 2007 | ISCAS | Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. | Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo |
| 2006 | FPL | Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. | Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly |
| 2005 | RSP | Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. | Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo |
| 2004 | FPL | Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. | Mario Garca-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo |
| 2000 | RSP | Highly Configurable Control Boards: A Tool and a Design Experience. | Eduardo de la Torre, Teresa Riesgo, Javier Uceda, E. Macip, M. Rizzi |
| 1998 | DATE | Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. | Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda |
| 1993 | ITC | Distributed Implementation of an ATPG System Using Dynamic Fault Allocation. | Maria Jos Aguado, Eduardo de la Torre, Miguel Miranda, Carlos A. Lpez-Barrio |