| 2017 | CHES | Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes. | Ins Ben El Ouahma, Quentin L. Meunier, Karine Heydemann, Emmanuelle Encrenaz |
| 2015 | CARDIS | Efficient Design and Evaluation of Countermeasures against Fault Attacks Using Formal Verification. | Lucien Goubet, Karine Heydemann, Emmanuelle Encrenaz, Ronald De Keulenaer |
| 2014 | RSP | FSM-based properties and abstraction of components. | Syed Hussein Syed Alwi, Emmanuelle Encrenaz |
| 2013 | EuroPar | A Formally Verified Static Hypervisor with Hardware Support for a Many-Core Chip. | Geoffrey Plouviez, Emmanuelle Encrenaz, Franck Wajsbrt |
| 2013 | FDL | Verification of heterogeneous systems: Theory and industrial experiences. | Christoph Grimm, Emmanuelle Encrenaz |
| 2013 | FDTC | Electromagnetic Fault Injection: Towards a Fault Model on a 32-bit Microcontroller. | Nicolas Moro, Amine Dehbaoui, Karine Heydemann, Bruno Robisson, Emmanuelle Encrenaz |
| 2012 | FDL | An efficient refinement strategy exploiting component properties in a cegar process. | Syed Hussein Syed Alwi, Ccile Braunstein, Emmanuelle Encrenaz |
| 2012 | FDL | Efficient Refinement Strategy Exploiting Component Properties in a CEGAR Process. | Syed Hussein Syed Alwi, Ccile Braunstein, Emmanuelle Encrenaz |
| 2010 | FDL | Formal Verification of Timed VHDL Programs. | Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Le D, Emmanuelle Encrenaz, Patricia Renault |
| 2010 | PDP | A Polynomial Algorithm to Prove Deadlock-Freeness of Wormhole Networks. | Sami Taktak, Emmanuelle Encrenaz, Jean Lou Desbarbieux |
| 2006 | RSP | Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter. | Ccile Braunstein, Emmanuelle Encrenaz |
| 1998 | CATA | Modular model checking of VLSI designs described in VHDL. | Fahim Rahim-Sarwary, Emmanuelle Encrenaz, Michel Minoux, Rajesh K. Bawa |