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Farhad Mehdipour

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

21

Venues

12

Active years

1999–2019

Best venue rank

A*

Where they publish

Papers

21 indexed papers, newest first.

YearVenueTitleAuthors
2019DASCCommercial Security Scanning: Point-on-Sale (POS) Vulnerability and Mitigation Techniques.Bahman A. Sassani Sarrafpour, Rosario Del Pilar Soria Choque, Blake Mitchell Paul, Farhad Mehdipour
2019DASCAgentPi: An IoT Enabled Motion CCTV Surveillance System.Bahman A. Sassani Sarrafpour, Andrew David, Xiaosong Li, Farhad Mehdipour
2019ITNACSupercomputer Networks in the Datacenter: Benchmarking the Evolution of Communication Granularity from Macroscale down to Nanoscale.Firas Al-Ali, Thilina Doremure Gamage, Hewa W. T. S. Nanayakkara, Farhad Mehdipour, Sayan Kumar Ray
2016DASCFOG-Engine: Towards Big Data Analytics in the Fog.Farhad Mehdipour, Bahman Javadi, Aniket Mahanti
2016PSTAnalysis of NTP DRDoS attacks' performance effects and mitigation techniques.Bahman A. Sassani, Charly Abarro, Ivan Pitton, Craig Young, Farhad Mehdipour
2015FPGAExploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs (Abstract Only).Navid Rahmanikia, Amirali Amiri, Hamid Noori, Farhad Mehdipour
2014ASPDACPhysical-aware task migration algorithm for dynamic thermal management of SMT multi-core processors.Bagher Salami, Mohammadreza Baharani, Hamid Noori, Farhad Mehdipour
2014ISCAA Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias.Mostafa Said, Farhad Mehdipour, Kazuaki J. Murakami, Mohamed El-Sayed
2013ASPDACMD: Minimal path-based fault-tolerant routing in on-Chip Networks.Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Farhad Mehdipour
2013DSDImproving Performance and Fabrication Metrics of Three-Dimensional ICs by Multiplexing Through-Silicon Vias.Mostafa Said, Farhad Mehdipour, Mohamed El-Sayed
2012DSDA Three-Dimensional Integrated Accelerator.Farhad Mehdipour, Krishna Chaitanya Nunna, Koji Inoue, Kazuaki J. Murakami
2012FPLThermal-aware partitioning for 3D FPGAs.Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki J. Murakami
2010DATEMapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits.Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Irina Kataeva, Kazuaki J. Murakami, Hiroyuki Akaike, Akira Fujimaki
2009ASPDACA combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki J. Murakami
2008ASPDACDesign space exploration for a coarse grain accelerator.Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami
2008ISLPEDEnhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension.Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki J. Murakami
2007DATEInteractive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi
2006EUCCustom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi
2006FPLA Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor.Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani
2005DSDReducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems.Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
1999IJCNNAn efficient method for placement of VLSI designs with Kohonen map.Morteza Saheb Zamani, Farhad Mehdipour