| 2014 | COMSNETS | Message from steering committee. | Uday B. Desai, Giridhar D. Mandyam, Rajeev Shorey, G. Venkatesh |
| 1998 | VLSID | Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. | Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh |
| 1998 | VLSID | Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1998 | VLSID | Extensions to Programmable DSP architectures for Reduced Power Dissipation. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1997 | VLSID | Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1996 | DAC | Optimized Code Generation of Multiplication-free Linear Transforms. | Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar |
| 1996 | VLSID | Low power realization of FIR filters using multirate architectures. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | ASPDAC | Techniques for low power realization for FIR filters. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | ICCAD | Synthesis of multiplier-less FIR filters with minimum number of additions. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | VLSID | A new methodology for the design of low-cost fail safe circuits and networks. | B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh |
| 1993 | VLSID | State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. | Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar |
| 1992 | VLSID | A Behavioral Fault Simulator For Ideal. | Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh |
| 1991 | ITC | A Methodology for Designing Optimal Self-Checking Sequential Circuits. | Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar |
| 1986 | DAC | Reasoning about digital systems using temporal logic. | S. Bapat, G. Venkatesh |