| 2015 | FPL | Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems. | Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris |
| 2014 | ICINCO | Program-based and Model-based PLC Design Environment for Multicore FPGA Architectures. | Christoforos E. Economakos, Michael G. Skarpetis, George Economakos |
| 2013 | BIBE | Efficient C level hardware design for floating point biomedical DSP applications. | Harry Sidiropoulos, Efthymia Kazakou, Christoforos E. Economakos, George Economakos |
| 2012 | DSD | Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain. | Dimitris Bekiaris, George Economakos |
| 2012 | EuroPar | A Methodology for Efficient Use of OpenCL, ESL and FPGAs in Multi-core Architectures. | Alexandros Bartzas, George Economakos |
| 2010 | DATE | Construction of dual mode components for reconfiguration aware high-level synthesis. | George Economakos, Sotirios Xydis, Ioannis Koutras, Dimitrios Soudris |
| 2010 | ISCAS | Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology. | Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos |
| 2009 | DSD | Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. | George Economakos, Sotirios Xydis |
| 2009 | DSD | Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology. | George Kiokes, George Economakos, Angelos Amditis, Nikolaos K. Uzunoglu |
| 2008 | BIBE | Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis. | George Economakos |
| 2008 | DSD | A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis. | George Economakos, Sotirios Xydis |
| 2008 | ETFA | Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis. | Christoforos E. Economakos, George Economakos |
| 2007 | ICINCO | Run-time reconfigurable solutions for adaptive control applications. | George Economakos, Christoforos E. Economakos, Sotirios Xydis |
| 2006 | ISCAS | Behavioral synthesis with SystemC and PSL assertions for interface specification. | George Economakos |
| 2006 | ISCAS | Bit level architectural exploration technique for the design of low power multipliers. | George Economakos, Kostas Anagnostopoulos |
| 2001 | DATE | Behavioral synthesis with systemC. | George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou |
| 2001 | DSD | A Multi-Lingual Synthesis and Verification Environment. | George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos |
| 1998 | DATE | AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. | George Economakos, George K. Papakonstantinou, Panayotis Tsanakas |
| 1998 | SAC | Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs. | George Economakos, George K. Papakonstantinou, Panayotis Tsanakas |