Gerhard W. Dueck
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
22
Venues
10
Active years
2003–2020
Best venue rank
A*
Where they publish
Papers
22 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | DATE | Towards Exploring the Potential of Alternative Quantum Computing Architectures. | Arighna Deb, Gerhard W. Dueck, Robert Wille |
| 2020 | DSD | Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers. | Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler |
| 2020 | RC | Search-Based Transformation Synthesis for 3-Valued Reversible Circuits. | D. Michael Miller, Gerhard W. Dueck |
| 2019 | RC | Efficient Realization of Toffoli and NCV Circuits for IBM QX Architectures. | Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre Csar Rodrigues da Silva |
| 2018 | DSD | Optimization of Circuits for IBM's Five-Qubit Quantum Computers. | Gerhard W. Dueck, Anirban Pathak, Md. Mazder Rahman, Abhishek Shukla, Anindita Banerjee |
| 2016 | ISCAS | An extension of transformation-based reversible and quantum circuit synthesis. | Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller |
| 2016 | RC | A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. | Mathias Soeken, Gerhard W. Dueck, D. Michael Miller |
| 2015 | ECOOP | Metis: a smart memory allocator using historical reclamation information. | Shijie Xu, Qi Guo, Gerhard W. Dueck, David Bremner, Yang Wang |
| 2014 | RC | Minimal Designs of Reversible Sequential Elements. | Anindita Banerjee, Anirban Pathak, Gerhard W. Dueck |
| 2012 | CEC | An algorithm to find quantum templates. | Md. Mazder Rahman, Gerhard W. Dueck |
| 2012 | RC | Properties of Quantum Templates. | Md. Mazder Rahman, Gerhard W. Dueck |
| 2011 | RC | Optimization of Reversible Circuits Using Reconfigured Templates. | Md. Mazder Rahman, Gerhard W. Dueck, Anindita Banerjee |
| 2010 | DDECS | Synthesizing multiplier in reversible logic. | Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| 2010 | DDECS | Window optimization of reversible and quantum circuits. | Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| 2009 | DATE | Debugging of Toffoli networks. | Robert Wille, Daniel Groe, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
| 2009 | DSD | Synthesizing Reversible Circuits for Irreversible Functions. | D. Michael Miller, Robert Wille, Gerhard W. Dueck |
| 2009 | VLSID | Reversible Logic Synthesis with Output Permutation. | Robert Wille, Daniel Groe, Gerhard W. Dueck, Rolf Drechsler |
| 2008 | DATE | Quantified Synthesis of Reversible Logic. | Robert Wille, Hoang Minh Le, Gerhard W. Dueck, Daniel Groe |
| 2006 | CEC | Level Compaction in Quantum Circuits. | Dmitri Maslov, Gerhard W. Dueck |
| 2005 | DATE | Quantum Circuit Simplification Using Templates. | Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck |
| 2003 | DAC | A transformation based algorithm for reversible logic synthesis. | D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck |
| 2003 | ICCAD | Fredkin/Toffoli Templates for Reversible Logic Synthesis. | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |