Giacomo Valente
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
12
Venues
8
Active years
2015–2025
Best venue rank
A*
Where they publish
Papers
12 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ETS | Multi-Context Execution on a RISC-V Core for Mixed-Criticality Systems. | Leonardo Fazzini, Giacomo Valente, Fabio Federici, Matthew P. Corbett, Tania Di Mascio |
| 2024 | ICCD | SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations. | Vittoriano Muttillo, Vincenzo Stoico, Marco Santic, Giacomo Valente, Luigi Pomante, Daniele Frigioni |
| 2023 | DAC | Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs. | Gianluca Brilli, Giacomo Valente, Alessandro Capotondi, Paolo Burgio, T. Di Masciov, Paolo Valente, Andrea Marongiu |
| 2022 | DSD | Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project. | Federica Caruso, Tania Di Mascio, Daniele Frigioni, Luigi Pomante, Giacomo Valente, Stefano Delucchi, Paolo Burgio, Manuel Di Frangia, Luca Paganin, Chiara Garibotto, Damiano Vallocchia |
| 2021 | DSD | An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems. | Gabriella D'Andrea, Giacomo Valente, Luigi Pomante, Tania Di Mascio |
| 2021 | MIS4TEL | MONICA "On-the-Job" Technology-Enhanced Learning Environment: An Empirical Evaluation. | Federica Caruso, Tania Di Mascio, Sara Peretti, Luigi Pomante, Giacomo Valente |
| 2020 | DSD | Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow. | Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Hector Posadas, Javier Merino, Eugenio Villar |
| 2020 | DSD | Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project. | Luigi Pomante, Francesca Palumbo, Claudia Rinaldi, Giacomo Valente, Carlo Sau, Tiziana Fanni, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jir Kadlec, Pekka Jskelinen, Marcos Martinez de Alejandro, Jukka Saarinen, Tero Sntti, Maria Katiuscia Zedda, Victor Sanchez, Dip Goswami, Zaid Al-Ars, Ad de Beer |
| 2020 | RTSS | Work-In-Progress: Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges. | Gabriella D'Andrea, Giacomo Valente |
| 2018 | DSD | Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW Partitions. | Vittoriano Muttillo, Giacomo Valente, Luigi Pomante |
| 2016 | PDP | A Flexible Profiling Sub-System for Reconfigurable Logic Architectures. | Giacomo Valente, Vittoriano Muttillo, Luigi Pomante, Fabio Federici, Marco Faccio, Andrea Moro, Serenella Ferri, Carlo Tieri |
| 2015 | FPL | A framework for integrated monitoring of real-time embedded SoC. | Giacomo Valente |