| 2025 | ISCAS | Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs. | Gins Domnech-Asensi, Francisco Javier Andreo-Oliver, Ramn Ruiz Merino, Jos ngel Daz-Madrid |
| 2023 | ISCAS | A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. | Gins Domnech-Asensi, Ramn Ruiz Merino, Juan Zapata-Prez, Jos ngel Daz-Madrid |
| 2020 | DATE | High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors. | Gins Domnech-Asensi, Tom J. Kazmierski |
| 2020 | ISCAS | Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. | Jos ngel Daz-Madrid, Gins Domnech-Asensi, Ramn Ruiz Merino, Juan Zapata-Prez, Jos Javier Martnez |
| 2020 | ISCAS | Stability and Efficiency of Explicit Integration in Interconnect Analysis on GPUs. | Gins Domnech-Asensi, Tom J. Kazmierski |
| 2019 | FDL | Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors. | Gins Domnech-Asensi, Tom J. Kazmierski |
| 2019 | ISCAS | An Efficient Numerical Solution Technique for VLSI Interconnect Equations on Many-Core Processors. | Gins Domnech-Asensi, Tom J. Kazmierski |
| 2019 | ISCAS | Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications. | Pablo Rubio-Ibez, J. Javier Martnez-lvarez, Gins Domnech-Asensi |
| 2017 | ISCAS | An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. | Jos ngel Daz-Madrid, Gins Domnech-Asensi, Jos-Alejandro Lpez Alcantud, M. Oberst |
| 2016 | DASC | Proactive Intelligent System for Optimizing Traffic Signaling. | Ramon Sanchez-Iborra, Juan F. Ingls-Romero, Gins Domnech-Asensi, Jos-Luis Moreno-Cegarra, Mara-Dolores Cano |
| 2014 | FPL | Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm. | Pablo Leyva, Gins Domnech-Asensi, F. Javier Garrigs, Julio Illade-Quinteiro, Vctor M. Brea, Paula Lpez, Diego Cabello |
| 2009 | DATE | Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. | Jos ngel Daz-Madrid, Harald Neubauer, Hans Hauer, Gins Domnech-Asensi, Ramn Ruiz Merino |
| 2008 | ISCAS | Accurate and reusable macromodeling technique using a fuzzy-logic approach. | Gins Domnech-Asensi, Juan Hinojosa, Ramn Ruiz Merino, Jos ngel Daz-Madrid |
| 2007 | IWINAC | Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits. | Jos ngel Daz-Madrid, Pedro Monsalve-Campillo, Juan Hinojosa, Mara Victoria Rodellar Biarge, Gins Domnech-Asensi |
| 2006 | FPL | Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. | Gins Domnech-Asensi, Juan Martnez-Alajarn, Ramn Ruiz Merino, Jos-Alejandro Lpez Alcantud |
| 2005 | IWINAC | Description and Simulation of Bio-inspired Systems Using VHDL-AMS. | Gins Domnech-Asensi, Jos-Alejandro Lpez Alcantud, Ramn Ruiz Merino |
| 2003 | IWANN | Current Mode CMOS Synthesis of a Motor-Control Neural System. | Gins Domnech-Asensi, Ramn Ruiz Merino, Hans Hauer, Jos ngel Daz-Madrid |