| 2025 | DATE | MPTorch-FPGA: A Custom Mixed-Precision Framework for FPGA-Based DNN Training. | Sami Ben Ali, Silviu-Ioan Filip, Olivier Sentieys, Guy G. Lemieux |
| 2011 | FPGA | VEGAS: soft vector processor with scratchpad memory. | Christopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G. Lemieux |
| 2011 | FPGA | A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements. | David Grant, Chris C. Wang, Guy G. Lemieux |
| 2011 | FPGA | The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. | Jonathan Rose, Guy G. Lemieux |
| 2011 | FPGA | Scalable and deterministic timing-driven parallel placement for FPGAs. | Chris C. Wang, Guy G. Lemieux |
| 2010 | FPGA | The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). | Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton |
| 2009 | FPGA | PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. | Johnny Tsung Lin Ho, Guy G. Lemieux |
| 2009 | FPGA | Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
| 2009 | FPL | Replace: An incremental placement algorithm for field programmable gate arrays. | David Leong, Guy G. Lemieux |
| 2008 | FPGA | Extreme parallel architectures for the masses. | Tarek A. El-Ghazawi, Guy G. Lemieux |
| 2008 | FPGA | Designing with extreme parallelism. | Guy G. Lemieux, Tarek A. El-Ghazawi |
| 2008 | FPGA | Vector processing as a soft-core CPU accelerator. | Jason Yu, Guy G. Lemieux, Christopher Eagleston |
| 2007 | FPGA | GlitchLess: an active glitch minimization technique for FPGAs. | Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton |
| 2006 | FPL | Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. | David Grant, Scott Chin, Guy G. Lemieux |
| 2006 | ICCAD | Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. | Marvin Tom, David Leong, Guy G. Lemieux |
| 2005 | DAC | Logic block clustering of large designs for channel-width constrained FPGAs. | Marvin Tom, Guy G. Lemieux |
| 2005 | FPL | Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. | Anthony J. Yu, Guy G. Lemieux |
| 2002 | FPGA | Circuit design of routing switches. | Guy G. Lemieux, David M. Lewis |
| 2002 | FPL | Analytical Framework for Switch Block Design. | Guy G. Lemieux, David M. Lewis |
| 2001 | FPGA | Using sparse crossbars within LUT. | Guy G. Lemieux, David M. Lewis |
| 2000 | FPGA | Generating highly-routable sparse crossbars for PLDs. | Guy G. Lemieux, Paul Leventis, David M. Lewis |
| 2000 | ICPP | The NUMAchine Multiprocessor. | R. Grindley, Tarek S. Abdelrahman, Stephen Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic |
| 1998 | DAC | Design and Implementation of the NUMAchine Multiprocessor. | A. Grbic, Stephen Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic |