| 2026 | FPGA | Gatling-V: An FPGA-based RISC-V Vector Core with Single-Issue, Multiple In-Flight Instruction Execution. | Farid Chalabi, Guy Lemieux |
| 2025 | ARITH | Range Extension with Supernormals for Mixed-Precision 8-bit DNN Training. | Shing Wai Pun, Bozhang Bao, Silviu-Ioan Filip, Guy Lemieux, John V. Kim, Nazar Misyats, Nirvik Pande, Victor Ravain, Robert Sherrick |
| 2025 | FPL | Virtualization and Dynamic Reconfiguration of Custom Instruction Accelerators (CIA) in RISC-V Embedded Systems. | Bea Healy, Brandon Freiberger, Jonas Kuenstler, King Lok Chung, Emil Cozac, Meinhard Kissich, Gennadiy Knis, Ron Sass, Dirk Koch, Jan Gray, Guy Lemieux |
| 2020 | MICRO | Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training. | Dingqing Yang, Amin Ghasemazar, Xiaowei Ren, Maximilian Golub, Guy Lemieux, Mieszko Lis |
| 2015 | FPGA | Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only). | Shao Lin S. T. Tang, Guy Lemieux |
| 2014 | FPGA | Soft vector processors with streaming pipelines. | Aaron Severance, Joe Edwards, Hossein Omidian, Guy Lemieux |
| 2012 | FCCM | VENICE: A Compact Vector Processor for FPGA Applications. | Aaron Severance, Guy Lemieux |