H. C. Srinivasaiah
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
2002–2012
Best venue rank
National
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | VLSID | Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM. | H. C. Srinivasaiah |
| 2004 | VLSID | Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. | H. C. Srinivasaiah, Navakanta Bhat |
| 2002 | VLSID | Implant Dose Sensitivity of 0.1m CMOS Inverter Delay. | H. C. Srinivasaiah, Navakanta Bhat |