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Paper
Implant Dose Sensitivity of 0.1m CMOS Inverter Delay.
H. C. Srinivasaiah
,
Navakanta Bhat
Venue
National
VLSID
Year
2002
Proceedings
ASP-DAC/VLSI Design
DBLP record
conf/vlsid/SrinivasaiahB02 ↗
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