H. Peter Hofstee
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
26
Venues
19
Active years
1992–2025
Best venue rank
A*
Where they publish
Papers
26 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | VLDB | High Throughput GPU-Accelerated FSST String Compression. | Tim Anema, Joost Hoozemans, Zaid Al-Ars, H. Peter Hofstee |
| 2023 | SC | OctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications. | Zaid Al-Ars, Jakoba Petri-Koenig, Joost Hoozemans, Luc Dierick, H. Peter Hofstee |
| 2023 | SC | Tydi-lang: A Language for Typed Streaming Hardware. | Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten |
| 2023 | VLDB | An Intermediate Representation for Composable Typed Streaming Dataflow Designs. | Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten |
| 2022 | BMVC | Improving Gradient Paths for Binary Convolutional Neural Networks. | Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars |
| 2022 | ISPDC | Communication-Efficient Cluster Scalable Genomics Data Processing Using Apache Arrow Flight. | Tanveer Ahmad, Chengxin Ma, Zaid Al-Ars, H. Peter Hofstee |
| 2021 | ICANN | An Attention Module for Convolutional Neural Networks. | Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars |
| 2021 | IJCAI | AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression. | Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars |
| 2020 | IJCNN | NASB: Neural Architecture Search for Binary Convolutional Neural Networks. | Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee |
| 2020 | MICRO | ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation. | Christian Pinto, Dimitris Syrivelis, Michele Gazzetti, Panos K. Koutsovasilis, Andrea Reale, Kostas Katrinis, H. Peter Hofstee |
| 2019 | FCCM | A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model. | Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee |
| 2019 | FPL | Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow. | Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, H. Peter Hofstee |
| 2017 | VLDB | Analyzing In-Memory Hash Join: Granularity Matters. | Jian Fang, Jinho Lee, H. Peter Hofstee, Jan Hidders |
| 2009 | EuroPar | HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? | Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Trff |
| 2009 | EuroPar | The Next 25 Years of Computer Architecture? | H. Peter Hofstee |
| 2008 | SIGGRAPH | Rome Reborn. | Bernard D. Frischer, Dean Abernathy, Gabriele Guidi, Joel Myers, Cassie Thibodeau, Antonio Salvemini, Pascal Mller, H. Peter Hofstee, Barry Minor |
| 2007 | CLUSTER | The future of multi-core technologies. | Michael T. Clark, H. Peter Hofstee, Edward J. Barragy, Ian Buck, Stephen W. Keckler |
| 2006 | ASPDAC | Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. | Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel |
| 2006 | SC | Invited speakers II - Real-time supercomputing and technology for games and entertainment. | H. Peter Hofstee |
| 2005 | HPCA | Power Efficient Processor Architecture and The Cell Processor. | H. Peter Hofstee |
| 2002 | ICCD | Power-Constrained Microprocessor Design. | H. Peter Hofstee |
| 2000 | DAC | "Timing closure by design, " a high frequency microprocessor design methodology. | Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia |
| 1998 | ICCD | Design methodology for a 1.0 GHz microprocessor. | Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo |
| 1998 | ICCD | A 690 ps read-access latency register file for a GHz integer microprocessor. | Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki |
| 1998 | VTS | High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. | David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz |
| 1992 | MPC | Distributing a Class of Sequential Programs. | H. Peter Hofstee |