Hirofumi Shinohara
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
1993–2011
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | DAC | A closed-form expression for estimating minimum operating voltage (V | Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai |
| 2011 | ISLPED | 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V | Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai |
| 2008 | DAC | Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. | Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara |
| 2008 | ISLPED | Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. | Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara |
| 2005 | ICCAD | Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. | Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara |
| 1993 | ICCD | A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. | Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara |