| 2026 | ISCAS | A High-Compression SISO CNN Accelerator Chip for Low External Memory Access. | Jing Shiun Hu, Qi-Hua Lin, Che-Wei Lin, I-Chyn Wey |
| 2026 | ISCAS | High Energy Efficiency TCAM In-Memory Search Architecture with Pre-Determined Short-Circuit Current Cutoff. | Wei-Chieh Lee, Chen-Ming Lee, Chia-Wei Su, Chun-Fu Chen, I-Chieh Hsu, I-Chyn Wey, Tee Hui Teo, An-Yeu Andy Wu |
| 2021 | SNPD | Wearable Parkinson's Disease Finger Tapping Quantitative Evaluation Algorithm Combined with Impedance Sensing. | Jhih-Syong Fong, Ya-Hui Chuang, Fu-Sheng Yu, I-Chyn Wey, San-Fu Wang |
| 2008 | ISCAS | An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. | Huifei Rao, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu |
| 2007 | ISCAS | Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. | Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao |
| 2007 | ISCAS | Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. | Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu |
| 2006 | ISCAS | A portable all-digital pulsewidth control loop for SOC applications. | Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu |
| 2006 | ISCAS | A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. | Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu |
| 2005 | ISCAS | A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. | I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu |
| 2005 | ISCAS | A scalable DCO design for portable ADPLL designs. | Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu |
| 2003 | ISCAS | A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. | Hwang-Cherng Chow, I-Chyn Wey |
| 2002 | ISCAS | A 3.3 V 1 GHz high speed pipelined Booth multiplier. | Hwang-Cherng Chow, I-Chyn Wey |