| 2010 | DATE | Panel: Reliability of data centers: Hardware vs. software. | Mehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota |
| 2009 | ETS | Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. | Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar |
| 2008 | DSN | Silent Data Corruption - Myth or reality? | Cristian Constantinescu, Ishwar Parulkar, R. Harper, Sarah Michalak |
| 2008 | ITC | DFX of a 3 | Ishwar Parulkar, Sriram Anandakumar, Gaurav Agarwal, Gordon Liu, Krishna Rajan, Frank Chiu, Rajesh Pendurkar |
| 2005 | IOLTS | Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems. | Ishwar Parulkar, Robert Cypher |
| 2005 | ITC | Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field. | Ishwar Parulkar, Dawei Huang, Leandro Chua Jr., Drew Doblar |
| 2005 | ITC | Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems. | Iain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski |
| 2003 | ITC | Latch Divergency In Microprocessor Failure Analysis. | Peter Dahlgren, Paul Dickinson, Ishwar Parulkar |
| 2002 | ITC | A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC | Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar |
| 1998 | DAC | Introducing Redundant Computations in a Behavior for Reducing BIST Resources. | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer |
| 1998 | DATE | Scheduling and Module Assignment for Reducing Bist Resources. | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer |
| 1996 | DAC | Lower Bounds on Test Resources for Scheduled Data Flow Graphs. | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer |
| 1995 | DAC | Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer |
| 1994 | DAC | Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. | Ishwar Parulkar, Melvin A. Breuer, Charles Njinda |