| 2026 | DATE | FiCABU: A Fisher-Based, Context-Adaptive Machine Unlearning Processor for Edge AI. | Eun-Su Cho, Jongin Choi, Jeongmin Jin, Jae-Jin Lee, Woojoo Lee |
| 2026 | DATE | Dynamic Neural Thresholding on Mixed-Signal Neuromorphic Processors Enabled by Integrated Learning and Hardware Design. | Kyuseung Han, Kwang-Il Oh, Sukho Lee, Hyeonguk Jang, Jae-Jin Lee, Sooyoung Jang |
| 2026 | DATE | LoRA-Edge: Tensor-Train-Assisted LoRA for Practical CNN Fine-Tuning on Edge Devices. | Hyunseok Kwak, Kyeongwon Lee, Jae-Jin Lee, Woojoo Lee |
| 2025 | FPL | NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA Prototyping. | Kyuseung Han, Hyeonguk Jang, Sukho Lee, Sung-Eun Kim, Kyudong Hwang, Jae-Jin Lee |
| 2025 | FPL | NeuGEMM: A Reordering-Free Unified GEMM-Conv2D Accelerator for Lightweight Neuromorphic Processors. | Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han |
| 2025 | ISLPED | ASAP-FE: Energy-Efficient Feature Extraction Enabling Multi-Channel Keyword Spotting on Edge Processors. | Jongin Choi, Jina Park, Jae-Jin Lee, Massoud Pedram, Woojoo Lee |
| 2024 | ISLPED | STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs. | Kyuseung Han, Hyunseok Kwak, Kwang-Il Oh, Sukho Lee, Hyeonguk Jang, Jae-Jin Lee, Woojoo Lee |
| 2023 | DATE | Developing an Ultra-low Power RISC-V Processor for Anomaly Detection. | Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee |
| 2023 | ISLPED | Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU. | Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram |
| 2019 | ISLPED | TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform. | Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram |
| 2008 | APNOMS | Service Impact Analysis Framework Using Service Model for Integrated Service Resource Management of NGN Services. | Seung Hee Han, Bom Soo Kim, Chan Kyou Hwang, Jae-Jin Lee |
| 2008 | ISCAS | A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder. | Jun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park |
| 2005 | ASPDAC | Design of an application-specific PLD architecture. | Jae-Jin Lee, Gi-Yong Song |
| 2004 | FPGA | Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. | Jae-Jin Lee, Gi-Yong Song |
| 2003 | ASPDAC | Implementation of the super-systolic array for convolution. | Jae-Jin Lee, Gi-Yong Song |