| 2012 | ASPDAC | Design for manufacturability and reliability for TSV-based 3D ICs. | David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang |
| 2012 | ICCAD | Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). | Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan |
| 2011 | ASPDAC | Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. | Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan |
| 2011 | DAC | Layout aware line-edge roughness modeling and poly optimization for leakage minimization. | Yongchan Ban, Jae-Seok Yang |
| 2011 | ICCAD | Chemical-mechanical polishing aware application-specific 3D NoC design. | Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan |
| 2010 | ASPDAC | A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. | Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan |
| 2010 | DAC | TSV stress aware timing analysis with applications to 3D-IC layout optimization. | Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan |
| 2010 | ICCAD | Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. | Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim |
| 2008 | ICCAD | Overlay aware interconnect and timing variation modeling for double patterning technology. | Jae-Seok Yang, David Z. Pan |