| 2026 | ICPR | SERC: LDPC-Inspired Semantic Error Correction for Retrieval-Augmented Generation. | Gyumin Kim, Juhwan Park, Jaeha Kim, Seunggyun Han, Kyungrak Son, Ikbeom Jang |
| 2025 | ASPDAC | WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory. | Seoyoon Jang, Sangouk Jeon, Kwanghyun Shin, Dongkwon Lee, Hankyu Chi, Wookjin Shin, Changhyun Pyo, Jaeha Kim, Dongsuk Jeon |
| 2025 | ASPDAC | Invited paper: Modeling and Simulation of Silicon Photonics Systems in SystemVerilog/XMODEL. | Jaeha Kim |
| 2025 | ICCV | Exploiting Diffusion Prior for Task-Driven Image Restoration. | Jaeha Kim, Junghun Oh, Kyoung Mu Lee |
| 2024 | CVPR | Beyond Image Super-Resolution for Image Recognition with Task-Driven Perceptual Loss. | Jaeha Kim, Junghun Oh, Kyoung Mu Lee |
| 2023 | CVPR | Recovering 3D Hand Mesh Sequence from a Single Blurry Image: A New Dataset and Temporal Unfolding. | Yeonguk Oh, JoonKyu Park, Jaeha Kim, Gyeongsik Moon, Kyoung Mu Lee |
| 2020 | ICCAD | Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations. | Nayoung Choi, Jaeha Kim |
| 2014 | DAC | Probabilistic Bug Localization via Statistical Inference based on Partially Observed Data. | Sangho Youn, Chenjie Gu, Jaeha Kim |
| 2014 | ITC | A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers. | Myeong-Jae Park, Jaeha Kim |
| 2013 | DAC | An event-driven simulation methodology for integrated switching power supplies in SystemVerilog. | Ji-Eun Jang, Myeong-Jae Park, Jaeha Kim |
| 2013 | ICCAD | Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization. | Taehwan Kim, Do-Gyoon Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim |
| 2013 | ISCAS | Robust random chip ID generation with wide-aperture clocked comparators and maximum likelihood detection. | Yunju Choi, Jaeha Kim |
| 2012 | DAC | Variability-aware, discrete optimization for analog circuits. | Seobin Jung, Yunju Choi, Jaeha Kim |
| 2012 | ISCAS | A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs. | Jaeha Kim, Sigang Ryu, Byoung-Joo Yoo, Hanseok Kim, Yunju Choi, Deog-Kyoon Jeong |
| 2011 | DAC | Global convergence analysis of mixed-signal systems. | Sangho Youn, Jaeha Kim, Mark Horowitz |
| 2010 | DAC | An efficient test vector generation for checking analog/mixed-signal functional models. | ByongChan Lim, Jaeha Kim, Mark A. Horowitz |
| 2010 | DATE | Intent-leveraged optimization of analog circuits via homotopy. | Metha Jeeradit, Jaeha Kim, Mark Horowitz |
| 2009 | CAV | Mixed-Signal System Verification: A High-Speed Link Example. | Jaeha Kim |
| 2009 | DAC | Stochastic steady-state and AC analyses of mixed-signal systems. | Jaeha Kim, Jihong Ren, Mark A. Horowitz |
| 2008 | ICCAD | Impulse sensitivity function analysis of periodic circuits. | Jaeha Kim, Brian S. Leibowitz, Metha Jeeradit |
| 2007 | DAC | Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch. | Jaeha Kim, Kevin D. Jones, Mark A. Horowitz |
| 2007 | ICCAD | Variable domain transformation for linear PAC analysis of mixed-signal systems. | Jaeha Kim, Kevin D. Jones, Mark A. Horowitz |
| 2003 | DAC | Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. | John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas |