| 2002 | ITC | A Multi-Language Goal-Tree Based Functional Test Planning System. | Rajneesh Mahajan, Ramesh Govindarajulu, James R. Armstrong, F. Gail Gray |
| 1998 | ITC | A goal tree based high-level test planning system for DSP real number models. | Morris Lin, James R. Armstrong, F. Gail Gray |
| 1995 | ICASSP | Efficient approaches to testing VHDL DSP models. | James R. Armstrong |
| 1994 | ITC | B-algorithm: A Behavioral-Test Generation Algorithm. | Chang Hyun Cho, James R. Armstrong |
| 1992 | ICCAD | Timing distribution in VHDL behavioral models. | Ashish S. Gadagkar, James R. Armstrong |
| 1990 | DAC | Behavioral Fault Simulation in VHDL. | P. C. Ward, James R. Armstrong |
| 1990 | RSP | Automated assists to the behavioral modeling process. | James R. Armstrong, D. Burnette |
| 1986 | DAC | A heuristic chip-level test generation algorithm. | Daniel S. Barclay, James R. Armstrong |
| 1985 | DAC | Functional fault modeling and simulation for VLSI devices. | Anil K. Gupta, James R. Armstrong |
| 1981 | DAC | GSP: A logic simulator for LSI. | James R. Armstrong, D. E. Devlin |
| 1977 | DAC | Simulation techniques for microprocessors. | James R. Armstrong, Garry W. Woodruff |