| 2026 | DDECS | FRAPPE: Feasibility Report on Accelerating Payload Pattern-Matching Engines in Intrusion Detection Systems with FPGAs. | Luks Sismis, Jan Korenek |
| 2024 | FCCM | LGBM2VHDL: Mapping of LightGBM Models to FPGA. | Toms Martnek, Jan Korenek, Toms Cejka |
| 2023 | DDECS | Optimizing Packet Classification on FPGA. | Michal Kekely, Jan Korenek |
| 2023 | INFOCOM | 400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs. | Jakub Cabal, Vladislav Vlek, Martin Spinler, Daniel Kondys, Jan Korenek |
| 2023 | ISCC | Accelerating IDS Using TLS Pre-Filter in FPGA. | Vlastimil Kosar, Luks Sismis, Jir Matousek, Jan Korenek |
| 2023 | PAM | Analysis of TLS Prefiltering for IDS Acceleration. | Luks Sismis, Jan Korenek |
| 2022 | FPL | FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit. | Jakub Cabal, Jiri Sikora, Stepn Friedl, Martin Spinler, Jan Korenek |
| 2021 | DDECS | Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis. | Roman Vrna, Jan Korenek |
| 2021 | ISCC | Scalability of Hash-Based Pattern Matching for High-Speed Network Security and Monitoring. | Toms Fukac, Jan Korenek, Jir Matousek |
| 2020 | DSD | Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. | Luks Kekely, Jakub Cabal, Viktor Pus, Jan Korenek |
| 2020 | LCN | Increasing Throughput of Intrusion Detection Systems by Hash-Based Short String Pre-filter. | Toms Fukac, Vlastimil Kosar, Jan Korenek, Jir Matousek |
| 2019 | DDECS | Hash-based Pattern Matching for High Speed Networks. | Tomas Fukac, Jan Korenek |
| 2019 | DDECS | Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic. | Roman Vrana, Jan Korenek, David Novak |
| 2019 | FCCM | Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata. | Milan Ceska, Vojtech Havlena, Luks Holk, Jan Korenek, Ondrej Lengl, Denis Matousek, Jir Matousek, Jakub Semric, Toms Vojnar |
| 2018 | DSD | Memory Aware Packet Matching Architecture for High-Speed Networks. | Michal Kekely, Lukas Kekely, Jan Korenek |
| 2018 | FCCM | High-Speed Regular Expression Matching with Pipelined Memory-Based Automata. | Denis Matousek, Jir Matousek, Jan Korenek |
| 2018 | FPGA | Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. | Jakub Cabal, Pavel Bencek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek |
| 2018 | FPL | Accelerated Wire-Speed Packet Capture at 200 Gbps. | Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek |
| 2018 | ICCD | General IDS Acceleration for High-Speed Networks. | Jan Kucera, Lukas Kekely, Adam Piecek, Jan Korenek |
| 2018 | NOMS | Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers. | Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek |
| 2017 | DSD | Packet Classification with Limited Memory Resources. | Michal Kekely, Jan Korenek |
| 2017 | FPL | Line rate programmable packet processing in 100Gb networks. | Pavel Bencek, Viktor Pus, Jan Korenek, Michal Kekely |
| 2017 | FPL | Mapping of P4 match action tables to FPGA. | Michal Kekely, Jan Korenek |
| 2016 | DSD | Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA. | Vlastimil Kosar, Jan Korenek |
| 2016 | FPL | Packet processing on FPGA SoC with DPDK. | Jan Viktorin, Jan Korenek |
| 2015 | DSD | Towards Efficient Field Programmable Pattern Matching Array. | Vlastimil Kosar, Jan Korenek |
| 2015 | IM | Hardware accelerated flow measurement of 100 Gb ethernet. | Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minark |
| 2014 | DDECS | Low latency book handling in FPGA for high frequency trading. | Milan Dvorak, Jan Korenek |
| 2014 | DDECS | Fast lookup for dynamic packet filtering in FPGA. | Lukas Kekely, Martin Zdnk, Jir Matousek, Jan Korenek |
| 2014 | DDECS | On NFA-split architecture optimizations. | Vlastimil Kosar, Jan Korenek |
| 2014 | DDECS | Design methodology of configurable high performance packet parser for FPGA. | Viktor Pus, Lukas Kekely, Jan Korenek |
| 2014 | FPL | Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. | Lukas Kekely, Viktor Pus, Pavel Bencek, Jan Korenek |
| 2014 | INFOCOM | Software Defined Monitoring of application protocols. | Lukas Kekely, Viktor Pus, Jan Korenek |
| 2013 | DDECS | Hardware architecture for the fast pattern matching. | Jan Kastil, Vlastimil Kosar, Jan Korenek |
| 2013 | DDECS | Hardware acceleration in computer networks. | Jan Korenek |
| 2013 | DDECS | Towards hardware architecture for memory efficient IPv4/IPv6 Lookup in 100 Gbps networks. | Jir Matousek, Martin Skacan, Jan Korenek |
| 2013 | FPL | Memory efficient IP lookup in 100 GBPS networks. | Jir Matousek, Martin Skacan, Jan Korenek |
| 2012 | IWCMC | Reducing memory in high-speed packet classification. | Viktor Pus, Jan Korenek |
| 2011 | DDECS | Reduction of FPGA resources for regular expression matching by relation similarity. | Vlastimil Kosar, Jan Korenek |
| 2011 | DDECS | Hardware architecture for packet classification with prefix coloring. | Viktor Pus, Michal Kajan, Jan Korenek |
| 2011 | DDECS | Effective hash-based IPv6 longest prefix match. | Jiri Tobola, Jan Korenek |
| 2010 | DDECS | Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing. | Jan Kastil, Jan Korenek |
| 2010 | DDECS | Efficient mapping of nondeterministic automata to FPGA for fast regular expression matching. | Jan Korenek, Vlastimil Kosar |
| 2010 | DDECS | Memory optimizations for packet classification algorithms in FPGA. | Viktor Pus, Juraj Blaho, Jan Korenek |
| 2009 | DDECS | Packet header analysis and field extraction for multigigabit networks. | Petr Kobiersk, Jan Korenek, Libor Polcak |
| 2009 | DSD | Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing. | Jan Kastil, Jan Korenek, Ondrej Lengl |
| 2009 | FPGA | Fast and scalable packet classification using perfect hash functions. | Viktor Pus, Jan Korenek |
| 2008 | DDECS | Network Probe for Flexible Flow Monitoring. | Martin Zdnk, Jan Korenek, Petr Kobiersk, Ondrej Lengl |
| 2008 | FPL | GICS: Generic interconnection system. | Tamas Malek, Toms Martnek, Jan Korenek |
| 2007 | DDECS | Intrusion Detection System Intended for Multigigabit Networks. | Jan Korenek, Petr Kobiersk |
| 2007 | DSD | Online Protocol Testing for FPGA Based Fault Tolerant Systems. | Jiri Tobola, Zdenek Kotsek, Jan Korenek, Toms Martnek, Martin Straka |
| 2007 | FPL | FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing. | Martin Kosek, Jan Korenek |
| 2006 | DDECS | A Flexible Technique for the Automatic Design of Approximate String Matching Architectures. | Toms Martnek, Jan Korenek, Otto Fuck, Matej Lexa |
| 2005 | FPL | NetFlow Probe Intended for High-Speed Networks. | Martin Zdnk, Tomas Pecenka, Jan Korenek |