| 2022 | ARITH | Low-Latency and High-Bandwidth Pipelined Radix-64 Division and Square Root Unit. | Javier D. Bruguera |
| 2022 | ARITH | Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking. | David M. Russinoff, Javier D. Bruguera, Cuong Chau, Mayank Manjrekar, Nicholas Pfister, Harsha Valsaraju |
| 2018 | ARITH | Radix-64 Floating-Point Divider. | Javier D. Bruguera |
| 2011 | ARITH | Composite Iterative Algorithm and Architecture for q-th Root Calculation. | lvaro Vzquez, Javier D. Bruguera |
| 2009 | DSD | Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. | Daniel Piso Fernandez, Javier D. Bruguera |
| 2009 | DSD | High Performance Image Processing on a Massively Parallel Processor Array. | Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera |
| 2008 | ACSSC | Forcing one-sided results in Goldschmidt algorithm. | Daniel Piso Fernandez, Javier D. Bruguera |
| 2008 | DSD | A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. | Daniel Piso Fernandez, Javier D. Bruguera |
| 2008 | EuroPar | Topic 10: Parallel Numerical Algorithms. | Hans-Joachim Bungartz, Javier D. Bruguera, Peter Arbenz, Bruce Hendrickson |
| 2006 | DSD | A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. | Javier D. Bruguera, Roberto R. Osorio |
| 2006 | DSD | A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. | Viay Holimath, Javier D. Bruguera |
| 2006 | DSD | A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. | Roberto R. Osorio, Javier D. Bruguera |
| 2005 | ARITH | Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. | Javier D. Bruguera, Toms Lang |
| 2005 | DSD | A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. | Roberto R. Osorio, Javier D. Bruguera |
| 2005 | WSCG | Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps. | F. J. Espino, Montserrat Bo, Margarita Amor, Javier D. Bruguera |
| 2004 | DSD | Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. | Roberto R. Osorio, Javier D. Bruguera |
| 2004 | WSCG | Algorithms and Hardware for Data Compression in Point Rendering Applications. | Paula N. Malln, Montserrat Bo, Margarita Amor, Javier D. Bruguera |
| 2003 | ARITH | High-Radix Iterative Algorithm for Powering Computation. | Jos-Alejandro Pieiro, Milos D. Ercegovac, Javier D. Bruguera |
| 2003 | ISCAS | On-line high-radix exponential with selection by rounding. | Jos-Alejandro Pieiro, Javier D. Bruguera, Milos D. Ercegovac |
| 2003 | WSCG | Adaptive Tessellation of NURBS Surfaces. | F. J. Espino, Montserrat Bo, Margarita Amor, Javier D. Bruguera |
| 2002 | DSD | Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. | Daniel Piso Fernandez, Jos-Alejandro Pieiro, Javier D. Bruguera |
| 2002 | ICCD | Floating-Point Fused Multiply-Add with Reduced Latency. | Toms Lang, Javier D. Bruguera |
| 2002 | ICCD | Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. | Jos-Alejandro Pieiro, Milos D. Ercegovac, Javier D. Bruguera |
| 2001 | ARITH | Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. | Javier D. Bruguera, Toms Lang |
| 2001 | ARITH | Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. | Jos-Alejandro Pieiro, Javier D. Bruguera, Jean-Michel Muller |
| 2001 | DSD | FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. | Jos-Alejandro Pieiro, Javier D. Bruguera, Jean-Michel Muller |
| 2001 | FPL | Implementation of a NURBS to Bzier Conversor with Constant Latency. | Paula N. Malln, Montserrat Bo, Javier D. Bruguera |
| 2000 | ICCD | Multilevel Reverse-Carry Adder. | Javier D. Bruguera, Toms Lang |
| 2000 | ISCAS | VLSI systolic array architecture for the lattice structure of the discrete wavelet transform. | Carlos E. Cabrera Reyes, Javier D. Bruguera |
| 1999 | ARITH | Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. | Elisardo Antelo, Toms Lang, Javier D. Bruguera |
| 1999 | ICCD | Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. | Toms Lang, Javier D. Bruguera |
| 1998 | ICCD | Leading-one prediction scheme for latency improvement in single datapath floating-point adders. | Javier D. Bruguera, Toms Lang |
| 1997 | ICASSP | VLSI implementation of an area-efficient architecture for the Viterbi algorithm. | Carlos Cabrera, Montserrat Bo, Javier D. Bruguera |
| 1996 | EuroPar | High Radix Cordic Rotation Based on Selection by Rounding. | Elisardo Antelo, Javier D. Bruguera, Toms Lang, Julio Villalba, Emilio L. Zapata |
| 1996 | ICIP | High performance VLSI architecture for the trellis coded quantization. | Montserrat Bo, Francisco Argello, Javier D. Bruguera, Emilio L. Zapata |
| 1995 | ARITH | Redundant CORDIC Rotator Based on Parallel Prediction. | Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata |
| 1995 | ICASSP | 2-D DCT using on-line arithmetic. | Javier D. Bruguera, Toms Lang |
| 1991 | ICASSP | Design of a constant geometry fast Hartley transformer. | Francisco Argello, Ramon Doallo, Javier D. Bruguera, Emilio L. Zapata |