| 2026 | DDECS | A SAT-Hard Compound Logic Locking Scheme with Empirical Resistance to Known Structural Attacks. | Sonali Shukla, Govind Rajhans Jadhav, Durgesh Sardan, Suryakant Toraskar, Jaynarayan T. Tudu, Makoto Ikeda, Masahiro Fujita, Virendra Singh |
| 2025 | ETS | SiFFS: A Scalable in-Fault Functional Simulation Framework for Fault Criticality Analysis. | Haripriya R. S, Naveen Kollepara, Jaynarayan T. Tudu |
| 2025 | HiPC | Distant History Branch Prediction Using Advanced Machine Learning Techniques. | Bonthu Purnanand, Jaynarayan T. Tudu |
| 2024 | HiPC | AI-Driven Power Gating for Enhanced Energy Efficiency in Superscalar Processors. | Naman Kalra, Jaynarayan T. Tudu |
| 2024 | VLSID | Near-Threshold-at-Gate based Test for Stuck-on Fault in Scan-chain Testing. | Haripriya R. S, Soumitro Vyapari, Jaynarayan T. Tudu |
| 2019 | IOLTS | Securing Scan through Plain-text Restriction. | Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh |
| 2018 | ISCAS | On Securing Scan Design Through Test Vector Encryption. | Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh |
| 2017 | IOLTS | Revisiting random access scan for effective enhancement of post-silicon observability. | Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh |
| 2016 | IOLTS | A high performance scan flip-flop design for serial and mixed mode scan test. | Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh |
| 2010 | ETS | Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara |
| 2009 | ETS | On Minimization of Peak Power for Scan Circuit during Test. | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal |