| 2026 | VTS | Innovative Practices Session: Recent Developments in IEEE Draft Standards P1687, P1687.2, and P2929. | Adam Cron, Stephen K. Sunter, Sankaran Menon, Jeff Rearick, Ilya Wagner, Tapan Chakraborty, Martin Keim |
| 2025 | ITC | Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges. | Hans Martin von Staudt, Jeff Rearick, Michael Laisne |
| 2023 | ITC | Welcome Message ITC 2023. | Li-C. Wang, Jeff Rearick |
| 2023 | VTS | Refreshing the JTAG Family. | Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg |
| 2022 | ITC | IEEE P1687.1: Extending the Network Boundaries for Test. | Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo |
| 2021 | ETS | Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces. | Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Michele Portolan, Martin Keim |
| 2020 | ETS | Linking Chip, Board, and System Test via Standards. | Michele Portolan, Jeff Rearick, Martin Keim |
| 2020 | ITC | Modeling Novel Non-JTAG IEEE 1687-Like Architectures. | Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick |
| 2020 | ITC | Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices. | Hans Martin von Staudt, Mohamed Anas Benhebibi, Jeff Rearick, Michael Laisne |
| 2019 | VTS | Innovative Practices on IEEE 1687.xyz. | Jeff Rearick, Alfred L. Crouch, Hans Martin von Staudt |
| 2018 | VTS | Innovative practices on quality levels of A/MS devices. | Wim Dobbelaere, On Semi, Massimo Violante, Turin Polytechnic, Jeff Rearick |
| 2017 | ITC | Maximizing scan pin and bandwidth utilization with a scan routing fabric. | Yan Dong, Grady Giles, GuoLiang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood |
| 2017 | ITC | Use models for extending IEEE 1687 to analog test. | Peter Sarson, Jeff Rearick |
| 2015 | ITC | Streaming fast access to ADCs and DACs for mixed-signal ATPG. | Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick |
| 2014 | ITC | Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns. | Sankar Gurumurthy, Mustansir Pratapgarhwala, Curtis Gilgan, Jeff Rearick |
| 2013 | ETS | Magical thinking applied to test engineering reality (and vice versa). | Jeff Rearick |
| 2012 | ETS | Re-using chip level DFT at board level. | Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson |
| 2011 | VTS | Structural tests of slave clock gating in low-power flip-flop. | Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick |
| 2010 | ITC | Vendor-agnostic native compression engine. | Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday |
| 2010 | VTS | Selecting the most relevant structural Fmax for system Fmax correlation. | Janine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja |
| 2009 | ITC | Cache-resident self-testing for I/O circuitry. | Sankar Gurumurthy, D. Bertanzetti, P. Jakobsen, Jeff Rearick |
| 2009 | ITC | IEEE P1687 IJTAG a presentation of current technology. | Ken Posse, Al Crouch, Jeff Rearick |
| 2008 | ITC | This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company. | Jeff Rearick |
| 2007 | ITC | Test cost reduction for the AMD™ Athlon processor using test partitioning. | Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick |
| 2006 | ITC | IEEE P1687: Toward Standardized Access of Embedded Instrumentation. | Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, Jean-Francois Cote |
| 2006 | ITC | A Survey of Test Problems and Solutions. | Jeff Rearick |
| 2006 | ITC | A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing. | Jeff Rearick, Aaron Volz |
| 2005 | ITC | IJTAG (internal JTAG): a step toward a DFT standard. | Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts |
| 2005 | ITC | Calibrating clock stretch during AC scan testing. | Jeff Rearick, Richard Rodgers |
| 2004 | ITC | Integrating Boundary Scan into Multi-GHz I/O Circuitry. | Jeff Rearick, Sylvia Patterson, Krista Dorner |
| 2003 | ITC | First IC Validation of IEEE Std. 1149.6. | Suzette Vandivier, Mark Wahl, Jeff Rearick |
| 2003 | VTS | Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. | Manish Sharma, Janak H. Patel, Jeff Rearick |
| 2001 | ITC | Frequency detection-based boundary-scan testing of AC coupled nets. | Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick |
| 2001 | ITC | Too much delay fault coverage is a bad thing. | Jeff Rearick |
| 2000 | ITC | Deception by design: fooling ourselves with gate-level models. | Peter C. Maxwell, Jeff Rearick |
| 1999 | ITC | Practical scan test generation and application for embedded FIFOs. | Jeff Rearick |
| 1998 | ITC | Estimation of defect-free IDDQ in submicron circuits using switch level simulation. | Peter C. Maxwell, Jeff Rearick |
| 1998 | ITC | Buying time for the stuck-at fault model. | Jeff Rearick |
| 1997 | ITC | The Case of Partial Scan. | Jeff Rearick |
| 1993 | ITC | Fast and Accurate CMOS Bridging Fault Simulation. | Jeff Rearick, Janak H. Patel |