| 2026 | FPGA | CAD-in-the-Cloud: Protecting FPGA Design Privacy via Redacted Netlists. | Eddie Rydell, Reilly McKendrick, Jeffrey Goeders |
| 2025 | ISCAS | Open-Source Circuit Radiation Effects (OSCRE) Simulation Framework: Design and Applications. | Collin Lambert, Jacob Anderson, David Nichols, Parker Allred, Sharisse Poff, Jeffrey Goeders, Michael J. Wirthlin, Shiuh-Hua Wood Chiang |
| 2024 | FPL | Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA. | Hayden Cook, Jeffrey Goeders |
| 2023 | FPL | Improving the Reliability of FPGA CRO PUFs. | Hayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders |
| 2021 | DATE | Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating Systems. | Benjamin James, Jeffrey Goeders |
| 2020 | FPL | Using Novel Configuration Techniques for Accelerated FPGA Aging. | Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings |
| 2019 | FPGA | On-chip FPGA Debug Instrumentation for Machine Learning Applications. | Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton |
| 2018 | FCCM | Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ. | Jeffrey Goeders, Tanner Gaskin, Brad L. Hutchings |
| 2018 | FPGA | Architecture Exploration for HLS-Oriented FPGA Debug Overlays. | Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton |
| 2018 | FPL | An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. | Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton |
| 2017 | FCCM | Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices. | Jeffrey Goeders |
| 2017 | FPL | Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. | Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton |
| 2016 | FPL | Quantifying observability for in-system debug of high-level synthesis circuits. | Jeffrey Goeders, Steven J. E. Wilton |
| 2012 | FPGA | The VTR project: architecture and CAD for FPGAs from verilog to routing. | Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson |