| 2006 | ASPDAC | Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. | Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen |
| 2006 | ISCAS | Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. | Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen |
| 2005 | ASPDAC | Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. | Jeng-Liang Tsai, Charlie Chung-Ping Chen |
| 2005 | ICCAD | Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. | Jeng-Liang Tsai, Lizheng Zhang |
| 2005 | VLSID | False Path and Clock Scheduling Based Yield-Aware Gate Sizing. | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
| 2004 | DATE | Thermal and Power Integrity Based Power/Ground Networks Optimization. | Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen |
| 2004 | ICCAD | HiSIM: hierarchical interconnect-centric circuit simulator. | Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik |
| 2004 | ICCAD | A yield improvement methodology using pre- and post-silicon statistical clock scheduling. | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |