Jens Leenstra
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
4
Active years
1989–2008
Best venue rank
A*
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | DAC | Scan chain clustering for test power reduction. | Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mding |
| 2007 | DAC | Scan Test Planning for Power Reduction. | Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mding, Jens Leenstra |
| 2006 | DATE | The vector fixed point unit of the synergistic processor element of the cell architecture processor. | Nicolas Mding, Jens Leenstra, Jrgen Pille, Rolf Sautter, Stefan Bttner, Sebastian Ehrenreich, W. Haller |
| 2006 | ITC | BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. | Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mding, Jens Leenstra |
| 2001 | ITC | Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. | Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schnemann, Thomas Schwarz, Hans-Joachim Wunderlich |
| 1997 | DAC | Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors. | Jrg A. Walter, Jens Leenstra, Gerhard Dttling, Bernd Leppla, Hans-Jrgen Mnster, Kevin W. Kark, Bruce Wile |
| 1991 | ITC | Hierarchical Test Program Development for Scan Testable Circuits. | Jens Leenstra, Lambert Spaanenburg |
| 1990 | ITC | Hierarchical test assembly for macro based VLSI design. | Jens Leenstra, Lambert Spaanenburg |
| 1989 | ICCD | Issues in the test of artificial neural networks. | Frank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg |
| 1989 | ITC | On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. | Jens Leenstra, Lambert Spaanenburg |