| 2010 | ISCAS | Multi-cycle compress technique for high-speed IP in low-cost environment. | Gong-Han Chen, Chu-Chuan Lin, Po-Han Wu, Jiann-Chyi Rau |
| 2010 | ISCAS | Multi-chains encoding scheme in low-cost ATE. | Gong-Han Chen, Po-Han Wu, Jiann-Chyi Rau |
| 2010 | ITC | The AB-filling methodology for power-aware at-speed scan testing. | Tsung-Tang Chen, Po-Han Wu, Kung-Han Chen, Jiann-Chyi Rau, Shih-Ming Tzeng |
| 2009 | ISCAS | Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression. | Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau |
| 2009 | ITC | Low power multi-chains encoding scheme for SoC in low-cost environment. | Po-Han Wu, Jiann-Chyi Rau |
| 2006 | ISCAS | A broadcast-based test scheme for reducing test size and application time. | Jiann-Chyi Rau, Jun-Yi Chang, Chien-Shiun Chen |
| 2005 | ISCAS | Reconfigurable multiple scan-chains for reducing test application time of SOCs. | Jiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma |
| 2005 | ISCAS | A novel reseeding mechanism for pseudo-random testing of VLSI circuits. | Jiann-Chyi Rau, Ying-Fu Ho, Po-Han Wu |
| 2002 | ISCAS | A don't-care based image circuit for function verification. | Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang |
| 2000 | ISCAS | A timing-driven pseudo-exhaustive testing of VLSI circuits. | Shih-Chieh Chang, Jiann-Chyi Rau |
| 2000 | ISCAS | A compact factored form for a Boolean function. | Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang |
| 1998 | ITC | A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. | Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu |