| 2020 | Tencon | Construction of Obstacle-Avoiding Delay-Driven GNR Routing Tree. | Jin-Tai Yan, Po-Yuan Huang, Chien-Yi Wang |
| 2014 | ISCAS | Feasible region assignment of routing nets in single-layer routing. | Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen |
| 2013 | ISCAS | Post-layout redundant wire insertion for fixing min-delay violations. | Jin-Tai Yan, Zhi-Wei Chen |
| 2012 | ICCD | Post-layout OPE-predicted redundant wire insertion for clock skew minimization. | Jin-Tai Yan, Zhi-Wei Chen |
| 2012 | ISCAS | Efficient assignment of inter-die signals for die-stacking SiP design. | Jin-Tai Yan, Chia-Han Kao, Ming-Chien Huang, Zhi-Wei Chen |
| 2011 | DATE | Timing-constrained I/O buffer placement for flip-chip designs. | Zhi-Wei Chen, Jin-Tai Yan |
| 2011 | DATE | Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance. | Jin-Tai Yan, Zhi-Wei Chen |
| 2011 | ICCD | Pre-assignment RDL routing via extraction of maximal net sequence. | Jin-Tai Yan, Zhi-Wei Chen |
| 2010 | ASPDAC | Obstacle-aware longest path using rectangular pattern detouring in routing grids. | Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen |
| 2010 | DAC | Two-sided single-detour untangling for bus routing. | Jin-Tai Yan, Zhi-Wei Chen |
| 2010 | ICCD | Routability-driven flip-flop merging process for clock power reduction. | Zhi-Wei Chen, Jin-Tai Yan |
| 2010 | ISCAS | Width-constrained wire sizing for non-tree interconnections. | Zhi-Wei Chen, Jin-Tai Yan |
| 2010 | ISCAS | Low-cost low-power bypassing-based multiplier design. | Jin-Tai Yan, Zhi-Wei Chen |
| 2009 | ASPDAC | IO connection assignment and RDL routing for flip-chip designs. | Jin-Tai Yan, Zhi-Wei Chen |
| 2009 | ISCAS | Accurate Transformation-based Timing Analysis for RC Non-tree Circuits. | Zhi-Wei Chen, Jin-Tai Yan, Hsing-Lin Ko |
| 2007 | ISCAS | Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity. | Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu |
| 2007 | VLSID | Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. | Jin-Tai Yan, Bo-Yi Chiang |
| 2006 | ISCAS | Timing-constrained yield-driven wire sizing for critical area minimization. | Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee |
| 2006 | ISCAS | Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. | Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang |
| 2006 | ISCAS | Optimal shielding insertion for inductive noise avoidance. | Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen |
| 2006 | ISCAS | Floorplan-aware decoupling capacitance budgeting on equivalent circuit model. | Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo |
| 2006 | VLSID | Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. | Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen |
| 2005 | ISCAS | Probabilistic congestion prediction in hierarchical quad-grid model. | Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu |
| 2005 | ISCAS | Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. | Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen |
| 2005 | ISCAS | Wiring area optimization in floorplan-aware hierarchical power grids. | Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen |
| 2005 | ISCAS | Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points. | Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee |
| 2004 | ASPDAC | Timing-constrained congestion-driven global routing. | Jin-Tai Yan, Shun-Hua Lin |
| 1996 | VLSID | A simple yet effective genetic approach for the orientation assignment on cell-based layout. | Jin-Tai Yan |
| 1995 | ASPDAC | Region definition and ordering assignment with the minimization of the number of switchboxes. | Jin-Tai Yan |
| 1995 | ICCD | Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning. | Jin-Tai Yan |
| 1995 | ICCD | An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. | Jin-Tai Yan |
| 1995 | VLSID | A new fuzzy-clustering-based approach for two-way circuit partitioning. | Jin-Tai Yan, Pei-Yung Hsiao |
| 1994 | ISCAS | Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing. | Paul-Waie Shew, Jin-Tai Yan, Pei-Yung Hsiao, Yong-Ching Lim |
| 1994 | ISCAS | Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment. | Jin-Tai Yan, Pei-Yung Hsiao |