John A. Nestor
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
6
Active years
1982–2010
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | ITiCSE | VCache: visualization applet for processor caches. | Berkin Ilbeyi, John A. Nestor |
| 2007 | FPL | L4: An FPGA-Based Accelerator for Detailed Maze Routing. | John A. Nestor, Jeremy Lavine |
| 2003 | FPL | FPGA Implementation of a Maze Routing Accelerator. | John A. Nestor |
| 1993 | ISCAS | SALSE II: A Fast Transformational Scheduler for High-level Synthesis. | Michael R. Rhinehart, John A. Nestor |
| 1992 | DAC | Data Path Allocation using an Extended Binding Model. | Ganesh Krishnamoorthy, John A. Nestor |
| 1990 | ICCAD | SALSA: A New Approach to Scheduling with Timing Constraints. | John A. Nestor, Ganesh Krishnamoorthy |
| 1989 | MICRO | MIES: a microarchitecture design tool. | John A. Nestor, Bassel Soudan, Zubair Mayet |
| 1988 | DAC | The System Architect's Workbench. | Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn |
| 1982 | DAC | Defining and implementing a multilevel design representation with simulation applications. | John A. Nestor, Donald E. Thomas |