| 2010 | ICCAD | Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis. | Nestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George I. Stamoulis, John Moondanos |
| 2006 | ASPDAC | Generation of shorter sequences for high resolution error diagnosis using sequential SAT. | Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna |
| 2004 | ASPDAC | Preserving synchronizing sequences of sequential circuits after retiming. | Maher N. Mneimneh, Karem A. Sakallah, John Moondanos |
| 2003 | DAC | A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. | Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna |
| 2001 | CAV | CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. | John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss |
| 1994 | VLSID | Verification of Circuits Described in VHDL through Extraction of Design Intent. | Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell |
| 1992 | ITC | Sequential Redundancy Identification Using Verification Techniques. | John Moondanos, Jacob A. Abraham |