| 2015 | IWANN | Stochastic-Based Implementation of Reservoir Computers. | Miquel L. Alomar, Vincent Canals, Vctor Martnez-Moll, Jos Luis Rossell |
| 2014 | IJCNN | Stochastic Spiking Neural Networks at the EDGE of CHAOS. | Jos Luis Rossell, Vicent Canals, Antoni Oliver, Antoni Morro |
| 2012 | IJCNN | Probabilistic-based neural network implementation. | Jos Luis Rossell, Vincent Canals, Antoni Morro |
| 2010 | IJCNN | Hardware implementation of stochastic-based Neural Networks. | Jos Luis Rossell, Vincent Canals, Antoni Morro |
| 2009 | ICANN | Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis. | Jos Luis Rossell, Ivan de Pal, Vincent Canals, Antoni Morro |
| 2009 | ISNN | Practical Hardware Implementation of Self-configuring Neural Networks. | Jos Luis Rossell, Vincent Canals, Antoni Morro, Ivan de Pal |
| 2008 | IJCNN | Using stochastic logic for efficient pattern recognition analysis. | Jos Luis Rossell, Vincent Canals, Ivan de Pal, Jaume Segura |
| 2007 | DATE | Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. | Jos Luis Rossell, Carol de Benito, Sebasti A. Bota, Jaume Segura |
| 2006 | DATE | A compact model to identify delay faults due to crosstalk. | Jos Luis Rossell, Jaume Segura |
| 2006 | IJCNN | A Fully CMOS Low-Cost Chaotic Neural Network. | Jos Luis Rossell, Sebasti A. Bota, Vicent Canals, Ivan de Pal, Jaume Segura |
| 2006 | VTS | Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. | Sebasti A. Bota, M. Rosales, Jos Luis Rossell, Jaume Segura |
| 2005 | DATE | Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. | Sebasti A. Bota, M. Rosales, Jos Luis Rossell, Jaume Segura |
| 2005 | DATE | A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. | Jos Luis Rossell, Vicent Canals, Sebasti A. Bota, Ali Keshavarzi, Jaume Segura |
| 2004 | DATE | A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. | Jos Luis Rossell, Jaume Segura |
| 2004 | ITC | Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. | Sebasti A. Bota, M. Rosales, Jos Luis Rossell, Jaume Segura, Ali Keshavarzi |
| 2001 | ICCAD | Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. | Jos Luis Rossell, Jaume Segura |