| 2026 | WCNC | PND3QN: A Deep Reinforcement Learning-driven Routing Selection Framework for Network-on-Chip. | Jingwen Wang, Fang Yu, Xuecheng Sun, Jos T. de Sousa, Jiao Li |
| 2024 | ARITH | PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. | Jos T. de Sousa, Joo D. Lopes, Micaela Serdio, Horcio C. Neto, Mrio P. Vstias |
| 2019 | FPL | Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. | Mrio P. Vstias, Rui Policarpo Duarte, Jos T. de Sousa, Horcio C. Neto |
| 2019 | ISCAS | Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. | Lus Fiolhais, Fernando M. Gonalves, Rui Policarpo Duarte, Mrio P. Vstias, Jos T. de Sousa |
| 2018 | FPL | Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. | Mrio P. Vstias, Rui Policarpo Duarte, Jos T. de Sousa, Horcio C. Neto |
| 2017 | FPL | K-means clustering on CGRA. | Joo D. Lopes, Jos T. de Sousa, Horcio C. Neto, Mrio P. Vstias |
| 2017 | FPL | Parallel dot-products for deep learning on FPGA. | Mrio P. Vstias, Rui Policarpo Duarte, Jos T. de Sousa, Horcio C. Neto |
| 2015 | ISCAS | An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications. | Marco Silva Pereira, Joo Caldinhas Vaz, Carlos Azeredo Leme, Jos T. de Sousa, Joo Costa Freire |
| 2005 | FPL | A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. | Victor Gonalves, Jos T. de Sousa, Fernando M. Gonalves |
| 2004 | FPL | Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. | Carlos J. Tavares, C. Bungardean, G. M. Matos, Jos T. de Sousa |
| 2003 | EPIA | Heuristic-Based Backtracking for Propositional Satisfiability. | Ateet Bhalla, Ins Lynce, Jos T. de Sousa, Joo Marques-Silva |
| 2003 | FPL | Fault Simulation Using Partially Reconfigurable Hardware. | Abilio Parreira, Joo Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, Jos T. de Sousa |
| 2002 | FCCM | On Implementing a Configware/Software SAT Solver. | N. A. Reis, Jos T. de Sousa |
| 2002 | FPL | DARP - A Digital Audio Reconfigurable Processor. | Jos T. de Sousa, Fernando M. Gonalves, Nuno Barreiro, Joo Moura |
| 2001 | FCCM | A Configurable Hardware/Software Approach to SAT Solving. | Jos T. de Sousa, J. M. da Silva, Miron Abramovici |
| 2000 | DATE | Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. | Jos T. de Sousa, Vishwani D. Agrawal |
| 1999 | DAC | A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. | Miron Abramovici, Jos T. de Sousa, Daniel G. Saab |
| 1999 | FCCM | A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. | Miron Abramovici, Jos T. de Sousa |
| 1997 | DATE | Improved diagnosis of realistic interconnect shorts. | Jos T. de Sousa, Peter Y. K. Cheung |
| 1996 | DATE | Realistic Fault Extraction for Boards. | Jos T. de Sousa, T. Shen, Peter Y. K. Cheung |
| 1992 | ITC | Physical DFT for High Coverage of Realistic Faults. | M. Saraiva, P. Casimiro, Marcelino B. Santos, Jos T. de Sousa, Fernando M. Gonalves, Isabel C. Teixeira, Joo Paulo Teixeira |
| 1991 | ITC | IC Defects-Based Testability Analysis. | Jos T. de Sousa, Fernando M. Gonalves, Joo Paulo Teixeira |