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Jos T. J. van Eijndhoven

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

18

Venues

9

Active years

1988–2006

Best venue rank

A*

Where they publish

Papers

18 indexed papers, newest first.

YearVenueTitleAuthors
2006DATECompositional, efficient caches for a chip multi-processor.Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
2005DATECompositional Memory Systems for Multimedia Communicating Tasks.Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
2004DATECompositional Memory Systems for Data Intensive Applications.Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven
2003HPCAInter-Cluster Communication Models for Clustered VLIW Processors.Andrei Sergeevich Terechko, Erwan Le Thenaff, Manish Garg, Jos T. J. van Eijndhoven, Henk Corporaal
2003VLSIDDesign of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar
2002ECRTSRobust Media Processing in a Flexible and Cost-Effective Network of Multi-Tasking Coprocessors.Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol
2002FCCMMPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64.Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2002FPLField-Programmable Custom Computing Machines - A Taxonomy -.Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers
2002ICCDSpeculative Trace Scheduling in VLIW Processors.Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan
2002PDPTAOn the Benefits of Speculative Trace Scheduling in VLIW Processors.Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan
2002VLSIDSystem-Level Design of Embedded Media Systems (Tutorial Abstract).Pieter van der Wolf, W. M. Kruijtzer, Jos T. J. van Eijndhoven
2001DATEPRMDL: a machine description language for clustered VLIW architectures.Andrei Sergeevich Terechko, Evert-Jan D. Pol, Jos T. J. van Eijndhoven
2001FCCMAn 8x8 IDCT Implementation on an FPGA-Augmented TriMedia.Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers
2001ICCDMPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor.Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
1999ICCDTriMedia CPU64 Architecture.Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel
1999ICCDTriMedia CPU64 Application Development Environment.Evert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndhoven, P. Struik, Pieter van der Wolf, Frans Sijstermans, M. J. A. Tromp, Jan-Willem van de Waerdt
1991ICCADFlexible Block-Multiplier Generation.H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon Stok
1988ICCADDoubly folded transistor matrix layout.Lukas P. P. P. van Genneken, Jos T. J. van Eijndhoven, Jos A. H. C. M. Brouwers