| 2025 | DATE | Multi-Partner Project: LoLiPoP-IoT - Design and Simulation of Energy-Efficient Devices for the Internet of Things. | Jakub Lojda, Josef Strnadel, Pavel Smrz, Vclav Simek |
| 2025 | DSD | Portable Simulation Models for Energy Aspects of IoT Devices in the LoLiPoP-IoT Project. | Jakub Lojda, Daire Joyce, Pavel Smrz, Shruti Kathuria, Josef Strnadel, Caitlin Quinn, Vclav Simek, Patrik Staron |
| 2024 | DSD | The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things. | Jakub Lojda, Josef Strnadel, Vclav Simek, Pavel Smrz, Mike Hayes, Ralf Popp |
| 2024 | VECoS | Using Statistical Model Checker for Schedulability Analysis of Real-Time Systems Under Uncertainty. | Josef Strnadel |
| 2024 | VECoS | On SMC-Based Dependability Analysis in LoLiPoP-IoT Project. | Josef Strnadel, Jakub Lojda, Pavel Smrz, Vclav Simek |
| 2022 | DDECS | Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. | Josef Strnadel |
| 2021 | DDECS | Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. | Josef Strnadel |
| 2020 | DATE | Statistical Model Checking of Approximate Circuits: Challenges and Opportunities. | Josef Strnadel |
| 2019 | DATE | Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates. | Josef Strnadel |
| 2018 | ISoLA | Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. | Josef Strnadel |
| 2017 | DSD | On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. | Josef Strnadel |
| 2016 | ISoLA | On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle. | Josef Strnadel |
| 2014 | DSD | Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. | Josef Strnadel, Martin Pokorny |
| 2013 | DDECS | On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems. | Josef Strnadel |
| 2012 | DDECS | Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems. | Josef Strnadel |
| 2012 | DSD | On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. | Josef Strnadel, Frantisek Slimarik |
| 2011 | DSD | On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. | Michal Rumplk, Josef Strnadel |
| 2010 | DDECS | Reduction of power dissipation through parallel optimization of test vector and scan register sequences. | Zdenek Kotsek, Jaroslav Skarvada, Josef Strnadel |
| 2010 | DSD | The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. | Zdenek Kotsek, Jaroslav Skarvada, Josef Strnadel |
| 2008 | DSD | TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. | Josef Strnadel |
| 2007 | DSD | Test Controller Synthesis Constrained by Circuit Testability Analysis. | Richard Ruzicka, Josef Strnadel |
| 2006 | DDECS | Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space. | Josef Strnadel |
| 2006 | DSD | Testability Estimation Based on Controllability and Observability Parameters. | Tomas Pecenka, Josef Strnadel, Zdenek Kotsek, Luks Sekanina |
| 2005 | DSD | Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. | Josef Strnadel, Zdenek Kotsek |
| 2004 | ISoLA | The Identification of registers in RTL Structures for the Test Application. | Daniel Mika, Josef Strnadel, Zdenek Kotsek |
| 2003 | DSD | Test scheduling for embedded systems. | Zdenek Kotsek, Daniel Mika, Josef Strnadel |
| 2002 | DSD | Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. | Josef Strnadel, Zdenek Kotsek |