| 2025 | ISCAS | An Accurate and Compact Design Integrating Seven Common Nonlinear Functions in Deep Learning. | Jye-En Wu, Ting-Wei Hu, Chih-Yao Liang, Juinn-Dar Huang |
| 2024 | ISCAS | A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications. | Meng-Hsun Hsieh, Xuan-Hong Li, Yu-Hsiang Huang, Pei-Hsuan Kuo, Juinn-Dar Huang |
| 2022 | ASPDAC | Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. | Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang |
| 2022 | MICCAI | Capture the Devil in the Details via Partition-then-Ensemble on Higher Resolution Images. | Yung-Han Chen, Yi-Jen Ju, Juinn-Dar Huang |
| 2021 | DSD | Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip. | Shuaijie Ying, Sudip Roy, Juinn-Dar Huang, Shigeru Yamashita |
| 2020 | ISCAS | High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme. | Yi-Lin Wu, Yi Lu, Juinn-Dar Huang |
| 2019 | ICCD | Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs. | Ling-Yen Song, Yi-Ling Chen, Yung-Chun Lei, Juinn-Dar Huang |
| 2018 | DATE | Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip. | Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang, Bhargab B. Bhattacharya |
| 2016 | ASPDAC | Chain-based pin count minimization for general-purpose digital microfluidic biochips. | Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou |
| 2015 | DATE | Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers. | Chi-Mei Huang, Chia-Hung Liu, Juinn-Dar Huang |
| 2014 | DATE | Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints. | Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang |
| 2013 | ICCAD | Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing. | Chia-Hung Liu, Hao-Han Chang, Tung-Che Liang, Juinn-Dar Huang |
| 2012 | FPGA | Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only). | Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang |
| 2012 | ICCAD | Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees. | Juinn-Dar Huang, Chia-Hung Liu, Ting-Wei Chiang |
| 2011 | ASPDAC | Throughput optimization for latency-insensitive system with minimal queue insertion. | Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho |
| 2011 | ASPDAC | Equivalence checking of scheduling with speculative code transformations in high-level synthesis. | Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou |
| 2011 | DATE | Architectural exploration of 3D FPGAs towards a better balance between area and delay. | Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang |
| 2009 | ASPDAC | CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. | Chia-I Chen, Juinn-Dar Huang |
| 2009 | ASPDAC | Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. | Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang |
| 2008 | ASPDAC | A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. | Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang |
| 2007 | ASPDAC | Fault Dictionary Size Reduction for Million-Gate Large Circuits. | Yu-Ru Hong, Juinn-Dar Huang |
| 2007 | ASPDAC | A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. | Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou |
| 2006 | ASPDAC | A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. | Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou |
| 2006 | ASPDAC | FSM-based transaction-level functional coverage for interface compliance verification. | Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou |
| 2004 | ITC | Verification on Port Connections. | Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang |
| 1998 | DAC | Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. | Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang |
| 1997 | ASPDAC | BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. | Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei |
| 1996 | ICCAD | An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
| 1995 | DAC | Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. | Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao |
| 1995 | ICCAD | Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |