Jwu E. Chen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
13
Venues
5
Active years
1990–2021
Best venue rank
A
Where they publish
Papers
13 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | ETS | Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. | Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu |
| 2021 | ITC | Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. | Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu |
| 2020 | DATE | Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. | Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen |
| 2020 | VTS | Innovative Practice on Wafer Test Innovations. | Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang |
| 2006 | ASPDAC | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. | Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen |
| 2006 | ITC | A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. | Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu |
| 2005 | ASPDAC | Oscillation ring based interconnect test scheme for SOC. | Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen |
| 2002 | DATE | An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. | Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen |
| 1999 | ETS | A DFT for semi-DC fault diagnosis for switched-capacitor circuits. | Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang, Jwu E. Chen |
| 1998 | ITC | Maximization of power dissipation under random excitation for burn-in testing. | Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen |
| 1998 | VTS | Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. | Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen |
| 1997 | VTS | Functional test pattern generation for CMOS operational amplifier. | Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen |
| 1990 | ITC | Single-fault fault collapsing analysis in sequential logic circuits. | Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen |