Kan Shi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
13
Venues
11
Active years
2013–2026
Best venue rank
A*
Where they publish
Papers
13 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | HPCA | TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification. | Yang Zhong, Haoran Wu, Xueqi Li, Sa Wang, David Boland, Yungang Bao, Kan Shi |
| 2026 | ISCA | Democratizing and Accelerating Hardware Verification with Software-Native Optimization. | Yunlong Xie, Zhicheng Yao, Fangyuan Song, Jincheng Liu, Junyue Wang, Haojin Tang, Lu Chen, Yinan Xu, Ziqing Zhang, Ziyuan Gao, Duan Yu, Hongtao Zhou, Jiayi Rao, Junyu Yue, Xiaolong Li, Yunqi Lu, Zechen Yang, Hang Zhu, Shan Liu, Xu An, Qi Ge, Jiuyue Ma, Jianyi Meng, Kan Shi, Dan Tang, Tianyi Liu, Sa Wang, Yungang Bao |
| 2025 | ASPDAC | Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration. | Zijian Jiang, Keran Zheng, David Boland, Yungang Bao, Kan Shi |
| 2025 | FPGA | Latency Insensitivity Testing for Dataflow HLS Designs. | Jianyi Cheng, Lianghui Wang, Zijian Jiang, Yungang Bao, Kan Shi |
| 2025 | FPGA | Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration. | Shuoxiang Xu, Zijian Jiang, Yuxin Zhang, David Boland, Yungang Bao, Kan Shi |
| 2025 | USENIX | Poby: SmartNIC-accelerated Image Provisioning for Coldstart in Clouds. | Zihao Chang, Jiaqi Zhu, Haifeng Sun, Yunlong Xie, Kan Shi, Ninghui Sun, Yungang Bao, Sa Wang |
| 2024 | ASPLOS | Hassert: Hardware Assertion-Based Verification Framework with FPGA Acceleration. | Ziqing Zhang, Weijie Weng, Yaning Li, Lijia Cai, Haoyu Wang, David Boland, Yungang Bao, Kan Shi |
| 2023 | FPGA | ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. | Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao |
| 2022 | FPL | Increasing Flexibility of Cloud FPGA Virtualization. | Jinjie Ruan, Yisong Chang, Ke Zhang, Kan Shi, Mingyu Chen, Yungang Bao |
| 2022 | MICRO | Towards Developing High Performance RISC-V Processors Using Agile Methodology. | Yinan Xu, Zihao Yu, Dan Tang, Guokai Chen, Lu Chen, Lingrui Gou, Yue Jin, Qianruo Li, Xin Li, Zuojun Li, Jiawei Lin, Tong Liu, Zhigang Liu, Jiazhan Tan, Huaqiang Wang, Huizhe Wang, Kaifan Wang, Chuanqi Zhang, Fawang Zhang, Linjuan Zhang, Zifei Zhang, Yangyang Zhao, Yaoyang Zhou, Yike Zhou, Jiangrui Zou, Ye Cai, Dandan Huan, Zusong Li, Jiye Zhao, Zihao Chen, Wei He, Qiyuan Quan, Xingwu Liu, Sa Wang, Kan Shi, Ninghui Sun, Yungang Bao |
| 2014 | DAC | Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. | Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides |
| 2013 | FCCM | Accuracy-Performance Tradeoffs on an FPGA through Overclocking. | Kan Shi, David Boland, George A. Constantinides |
| 2013 | ISCAS | Overclocking datapath for latency-error tradeoff. | Kan Shi, David Boland, George A. Constantinides |