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Karthikeyan Madathil

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

2

Venues

2

Active years

1999–2000

Best venue rank

National

Where they publish

Papers

2 indexed papers, newest first.

YearVenueTitleAuthors
2000VLSIDA Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar
1999ICCDA Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.