Karthikeyan Natarajan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
5
Active years
2011–2022
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ETS | Power Aware Test. | Likith Kumar Manchukonda, Karthikeyan Natarajan, Manish Arora |
| 2022 | ITC | Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs. | Khader S. Abdel-Hafez, Michael Dsouza, Likith Kumar Manchukonda, Elddie Tsai, Karthikeyan Natarajan, Ting-Pu Tai, Wenhao Hsueh, Smith Lai |
| 2022 | ITC | High Speed IO Access for Test forms the foundation for Silicon Lifecycle Management. | Amit Pandey, Brendan Tully, Karthikeyan Natarajan |
| 2022 | VTS | Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/O. | Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal |
| 2019 | DAC | High Performance Graph Convolutional Networks with Applications in Testability Analysis. | Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu |
| 2018 | HiPC | Lossless Parallel Implementation of a Turbo Decoder on GPU. | Karthikeyan Natarajan, Nitin Chandrachoodan |
| 2016 | VTS | Dynamic docking architecture for concurrent testing and peak power reduction. | Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha |
| 2016 | VTS | A programmable method for low-power scan shift in SoC integrated circuits. | Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani |
| 2011 | VTS | Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. | Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu |