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Kazuaki J. Murakami

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

32

Venues

18

Active years

1989–2015

Best venue rank

A*

Where they publish

Papers

32 indexed papers, newest first.

YearVenueTitleAuthors
2015VINCIInteractive Visualization of Quantitative Data with G2D3.Antoine Trouv, Kazuaki J. Murakami
2014ISCAA Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias.Mostafa Said, Farhad Mehdipour, Kazuaki J. Murakami, Mohamed El-Sayed
2013ICCSUsing Machine Learning in Order to Improve Automatic SIMD Instruction Generation.Antoine Trouv, Arnaldo J. Cruz, Hiroki Fukuyama, Jun Maki, Hadrien A. Clarke, Kazuaki J. Murakami, Masaki Arai, Tadashi Nakahira, Eiji Yamanaka
2013ICSMAD7: a memory architecture simulator targeted at design space exploration.Hadrien A. Clarke, Antoine Trouv, Kazuaki J. Murakami
2012DSDA Three-Dimensional Integrated Accelerator.Farhad Mehdipour, Krishna Chaitanya Nunna, Koji Inoue, Kazuaki J. Murakami
2012FPLThermal-aware partitioning for 3D FPGAs.Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki J. Murakami
2012OSDIPower and Performance Analysis of GPU-Accelerated Systems.Yuki Abe, Hiroshi Sasaki, Martin Peres, Koji Inoue, Kazuaki J. Murakami, Shinpei Kato
2011DSDThermal Effect of TSVs in 3D Die-Stacked Integrated Circuits.Hadrien A. Clarke, Kazuaki J. Murakami
2010DATEMapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits.Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Irina Kataeva, Kazuaki J. Murakami, Hiroyuki Akaike, Akira Fujimaki
2009ASPDACA combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki J. Murakami
2008ASPDACDesign space exploration for a coarse grain accelerator.Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami
2008ISLPEDEnhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension.Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki J. Murakami
2008SCPerformance prediction of large-scale parallell system and application using macro-level simulation.Ryutaro Susukita, Hisashige Ando, Mutsumi Aoyagi, Hiroaki Honda, Yuichi Inadomi, Koji Inoue, Shigeru Ishizuki, Yasunori Kimura, Hidemi Komatsu, Motoyoshi Kurokawa, Kazuaki J. Murakami, Hidetomo Shibamura, Shuji Yamamura, Yunqing Yu
2007DATEInteractive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi
2007DATETask scheduling for reliable cache architectures of multiprocessor systems.Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
2007SBAC-PADPerformance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms.Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki J. Murakami, Guilherme de Melo Baptista Domingues
2006EUCCustom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi
2006FPLA Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor.Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani
2006HiPCCollective Communication Costs Analysis over Gigabit Ethernet and InfiniBand.Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki J. Murakami
2006ISCASA character size optimization technique for throughput enhancement of character projection lithography.Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
2006SACPreliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications.Hamid Noori, Kazuaki J. Murakami
2002ICCDA Low Energy Set-Associative I-Cache with Extended BTB.Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami
2002ISLPEDA history-based I-cache for low-energy multimedia applications.Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami
2001ASPDACDevelopment of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication.Takanori Okuma, Koji Hashimoto, Kazuaki J. Murakami
1999HPCADynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs.Koji Inoue, Koji Kai, Kazuaki J. Murakami
1999ISLPEDWay-predicting set-associative cache for high performance and low energy consumption.Koji Inoue, Tohru Ishihara, Kazuaki J. Murakami
1999SCMOE: A Special-Purpose Parallel Computer for High-Speed, Large-Scale Molecular Orbital Calculation.Koji Hashimoto, Hiroto Tomita, Koji Inoue, Katsuhiko Metsugi, Kazuaki J. Murakami, Shinjiro Inabata, So Yamada, Nobuaki Miyakawa, Hajime Takashima, Kunihiro Kitamura, Shigeru Obara, Takashi Amisaki, Kazutoshi Tanabe, Umpei Nagashima
1998ISLPEDOptimizing the DRAM refresh count for merged DRAM/logic LSIs.Taku Ohsawa, Koji Kai, Kazuaki J. Murakami
1993ICSA Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking.Takashi Hashimoto, Kazuaki J. Murakami, Tetsuo Hironaka, Hiroto Yasuura
1992ICSBenchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture.Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki J. Murakami, Shinji Tomita
1989ISCASIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita
1989ICSThe Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures.Kazuaki J. Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita