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Keerthi Heragu

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

4

Active years

1994–2001

Best venue rank

A*

Where they publish

Papers

10 indexed papers, newest first.

YearVenueTitleAuthors
2001VTSTesting of Dynamic Logic Circuits Based on Charge Sharing.Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton
1999VLSIDA Test Generator for Segment Delay Faults.Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1998VTSWhere We Might Stumble with Embedded-System Test.Keerthi Heragu
1997ICCADFast identification of untestable delay faults using implications.Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996ICCADSIGMA: a simulator for segment delay faults.Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996VLSIDImproving accuracy in path delay fault coverage estimation.Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996VTSSegment delay faults: a new fault model.Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1995VLSIDStatistical methods for delay fault coverage analysis.Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
1994DACAn Efficient Path Delay Fault Coverage Estimator.Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
1994VTSFACTS: fault coverage estimation by test vector sampling.Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell