| 2007 | CHES | Masking and Dual-Rail Logic Don't Add Up. | Patrick Schaumont, Kris Tiri |
| 2007 | DAC | Side-Channel Attack Pitfalls. | Kris Tiri |
| 2007 | FSE | An Analytical Model for Time-Driven Cache Attacks. | Kris Tiri, Onur Aciimez, Michael Neve, Flemming Andersen |
| 2005 | CHES | Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. | Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede |
| 2005 | DAC | A side-channel leakage free coprocessor IC in 0.18m CMOS for embedded AES-based cryptographic and biometric processing. | Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede |
| 2005 | DAC | Simulation models for side-channel information leaks. | Kris Tiri, Ingrid Verbauwhede |
| 2005 | DATE | Design Method for Constant Power Consumption of Differential Logic Circuits. | Kris Tiri, Ingrid Verbauwhede |
| 2005 | DATE | A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. | Kris Tiri, Ingrid Verbauwhede |
| 2004 | CARDIS | Place and Route for Secure Standard Cell Design. | Kris Tiri, Ingrid Verbauwhede |
| 2004 | CASES | Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. | Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede |
| 2004 | DATE | A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. | Kris Tiri, Ingrid Verbauwhede |
| 2004 | FPL | Secure Logic Synthesis. | Kris Tiri, Ingrid Verbauwhede |
| 2003 | CHES | Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. | Kris Tiri, Ingrid Verbauwhede |
| 2002 | DAC | Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. | Mustafa Badaroglu, Kris Tiri, Stphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen |