Krishna Chakravadhanula
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
12
Venues
2
Active years
2008–2025
Best venue rank
A
Where they publish
Papers
12 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ITC | Pseudo-Random Low Power Built In Self Test. | Dale Meehl, Sameer Chillarige, Bharath Nandakumar, Carl Wisnesky, Krishna Chakravadhanula |
| 2022 | ITC | PPA Optimization of Test Points in Automotive Designs. | Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran |
| 2019 | ITC | Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. | Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula |
| 2018 | ITC | Improving Diagnosis Resolution and Performance at High Compression Ratios. | Sameer Chillarige, Atul Chhabra, Anil Malik, Bharath Nandakumar, Joe Swenton, Krishna Chakravadhanula |
| 2017 | ITC | Advancing test compression to the physical dimension. | Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox |
| 2017 | ITC | High throughput multiple device diagnosis system. | Sameer Chillarige, Anil Malik, Sharjinder Singh, Joe Swenton, Krishna Chakravadhanula |
| 2014 | ITC | Efficient testing of hierarchical core-based SOCs. | Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen |
| 2014 | VLSID | Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. | Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula |
| 2013 | ITC | SmartScan - Hierarchical test compression for pin-limited low power designs. | Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj |
| 2010 | ITC | Low cost at-speed testing using On-Product Clock Generation compatible with test compression. | Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise |
| 2009 | ITC | Capture power reduction using clock gating aware test generation. | Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang |
| 2008 | ITC | A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. | Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula |