| 2005 | DATE | An Efficient Sequential SAT Solver With Improved Search Strategies. | Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen |
| 1998 | DAC | Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu |
| 1997 | ASPDAC | AQUILA: An equivalence verifier for large sequential circuits. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen |
| 1997 | ITC | Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng |
| 1997 | VTS | Incremental logic rectification. | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng |
| 1996 | DAC | Error Correction Based on Verification Techniques. | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng |
| 1996 | DAC | Compact Vector Generation for Accurate Power Simulation. | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee |
| 1996 | DATE | Sequential Permissible Functions and their Application to Circuit Optimization. | Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee |
| 1996 | ISLPED | A novel methodology for transistor-level power estimation. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee |
| 1996 | ITC | An ATPG-Based Framework for Verifying Sequential Equivalence. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Glser |
| 1995 | ASPDAC | Logic rectification and synthesis for engineering change. | Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen |
| 1995 | DAC | Logic Synthesis for Engineering Change. | Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng |
| 1995 | FPGA | Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. | Anmol Mathur, Kuang-Chien Chen, C. L. Liu |
| 1995 | ICCAD | Cost-free scan: a low-overhead scan path design methodology. | Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen |
| 1995 | ICCAD | Re-engineering of timing constrained placements for regular architectures. | Anmol Mathur, Kuang-Chien Chen, C. L. Liu |
| 1992 | DAC | Efficient Sum-to-One Subsets Algorithm for Logic Optimization. | Kuang-Chien Chen, Masahiro Fujita |
| 1992 | ICCD | An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. | Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen |
| 1991 | DAC | A Resynthesis Approach for Network Optimization. | Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita |
| 1991 | ICCAD | Application of Boolean Unification to Combinational Logic Synthesis. | Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen |
| 1991 | ICCD | Concurrent Resynthesis for Network Optimization. | Kuang-Chien Chen, Masahiro Fujita |
| 1990 | DAC | Timing Optimization for Multi-Level Combinational Networks. | Kuang-Chien Chen, Saburo Muroga |
| 1989 | ICCAD | SYLON-DREAM: a multi-level network synthesizer. | Kuang-Chien Chen, Saburo Muroga |
| 1988 | ICCAD | Input assignment algorithm for decoded-PLAs with multi-input decoders. | Kuang-Chien Chen, Saburo Muroga |